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Volumn 4, Issue 4, 1999, Pages 376-404

A flexible datapath allocation method for architectural synthesis

Author keywords

Allocation and binding; High level synthesis

Indexed keywords


EID: 7944228490     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/323480.323486     Document Type: Article
Times cited : (9)

References (34)
  • 1
    • 0027099480 scopus 로고    scopus 로고
    • AND CHEN, C. Y. R. 1991. Post-processor for data path synthesis using multiport memories
    • 91, Santa Clara, CA, Nov. 11-14 IEEE Computer Society Press, Los Alamitos, CA, 276-279.
    • AHMAD, I. AND CHEN, C. Y. R. 1991. Post-processor for data path synthesis using multiport memories. In Proceedings of the IEEE I ACM International Conference on Computer-Aided Design (ICCAD '91, Santa Clara, CA, Nov. 11-14) IEEE Computer Society Press, Los Alamitos, CA, 276-279.
    • In Proceedings of the IEEE I ACM International Conference on Computer-Aided Design ICCAD '
    • Ahmad, I.1
  • 2
    • 0023998697 scopus 로고    scopus 로고
    • BANERJI, D. K., MAJUMDAR, A. K., LINDERS, J. G., and MAJITHIA, J. C. 1990. Allocation of multiport memories in data path synthesis
    • 7, 4 (Apr. 1990), 536-540.
    • BALAKRISHNAN, M., BANERJI, D. K., MAJUMDAR, A. K., LINDERS, J. G., AND MAJITHIA, J. C. 1990. Allocation of multiport memories in data path synthesis. IEEE Trans. Comput.-Aided Des. 7, 4 (Apr. 1990), 536-540.
    • IEEE Trans. Comput.-Aided Des.
    • Balakrishnan, M.1
  • 4
    • 0024706222 scopus 로고    scopus 로고
    • AND NEWTON, R. 1989. Algorithms for hardware allocation in data path Synthesis
    • 8, 7 (Jul. 1989), 768-781.
    • DEVADAS, S. AND NEWTON, R. 1989. Algorithms for hardware allocation in data path Synthesis. IEEE Trans. Comput.-Aided Des. 8, 7 (Jul. 1989), 768-781.
    • IEEE Trans. Comput.-Aided Des.
    • Devadas, S.1
  • 5
    • 0021784846 scopus 로고    scopus 로고
    • AND KERNIGHAN, B. W. 1985. a procedure for placement of standard-cell VLSI circuits
    • 4, 1 (Jan. 1985), 92-98.
    • DUNLOP, A. E. AND KERNIGHAN, B. W. 1985. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. Comput.-Aided Des. 4, 1 (Jan. 1985), 92-98.
    • IEEE Trans. Comput.-Aided Des.
    • Dunlop, A.E.1
  • 8
    • 0027660748 scopus 로고    scopus 로고
    • AND ELMASRY, M. I. 1993. Global optimization approach for architectural synthesis
    • 12, 9, 1266-1278.
    • GEBOTYS, C. H. AND ELMASRY, M. I. 1993. Global optimization approach for architectural synthesis. IEEE Trans. Comput.-Aided Des. 12, 9, 1266-1278.
    • IEEE Trans. Comput.-Aided Des.
    • Gebotys, C.H.1
  • 9
    • 0024645923 scopus 로고    scopus 로고
    • AND ELMASRY, M. I. 1989. Architectural synthesis for DSP silicon compilers
    • 8, 4 (Apr. 1989), 431-447.
    • HAROUN, B. S. AND ELMASRY, M. I. 1989. Architectural synthesis for DSP silicon compilers. IEEE Trans. Comput.-Aided Des. 8, 4 (Apr. 1989), 431-447.
    • IEEE Trans. Comput.-Aided Des.
    • Haroun, B.S.1
  • 10
    • 33746737777 scopus 로고    scopus 로고
    • LEVITAN, S. P, and PANGRLE, B. M. 1993. Incorporating interconnection delays in VHDL behavioral synthesis
    • 4th on ACMISIGDA Physical Design Workshop 175-186.
    • HSIEH, Y.-W., LEVITAN, S. P, AND PANGRLE, B. M. 1993. Incorporating interconnection delays in VHDL behavioral synthesis. In Proceedings of the 4th on ACMISIGDA Physical Design Workshop 175-186.
    • In Proceedings of the
    • Hsieh, Y.-W.1
  • 12
    • 0027839099 scopus 로고    scopus 로고
    • AND PANGRLE, B. M. 1993. a grid-based approach for connectivity binding with geometric costs
    • 93, Santa Clara, CA, Nov. 7-11, 1993, M. Lightner and J. A. G. Jess, Eds. IEEE Computer Society Press, Los Alamitos, CA, 94-99.
    • JANG, H.-J. AND PANGRLE, B. M. 1993. A grid-based approach for connectivity binding with geometric costs. In Proceedings of the International Conference on Computer-Aided Design (ICCAD '93, Santa Clara, CA, Nov. 7-11, 1993), M. Lightner and J. A. G. Jess, Eds. IEEE Computer Society Press, Los Alamitos, CA, 94-99.
    • In Proceedings of the International Conference on Computer-Aided Design ICCAD '
    • Jang, H.-J.1
  • 13
    • 84990479742 scopus 로고    scopus 로고
    • AND LIN, S. 1970. an efficient heuristic procedure for partitioning graphs
    • KERNIGIIAN, B. AND LIN, S. 1970. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. (Feb.).
    • Bell Syst. Tech. J. (Feb.).
    • Kernigiian, B.1
  • 14
    • 0027271160 scopus 로고    scopus 로고
    • AND LlU, C. L. 1993. Utilization of multiport memories in data path synthesis
    • 30th International Conference on Design Automation (DAC'93, Dallas, TX, June 14-18), A. E. Dunlop, Ed. ACM Press, New York, NY, 298-302.
    • KlM, T. AND LlU, C. L. 1993. Utilization of multiport memories in data path synthesis. In Proceedings of the 30th International Conference on Design Automation (DAC'93, Dallas, TX, June 14-18), A. E. Dunlop, Ed. ACM Press, New York, NY, 298-302.
    • In Proceedings of the
    • Klm, T.1
  • 15
    • 26444479778 scopus 로고    scopus 로고
    • GELATT, C. D., JR., and VECCHI, M. P. 1983. Optimization by simulated annealing
    • 220, 4598 (May), 671-680.
    • KIRKPATRICK, S., GELATT, C. D., JR., AND VECCHI, M. P. 1983. Optimization by simulated annealing. Science 220, 4598 (May), 671-680.
    • Science
    • Kirkpatrick, S.1
  • 16
    • 0025540324 scopus 로고    scopus 로고
    • Feedback-driven datapath optimization in Fasolt
    • 90 IEEE Computer Society Press, Los Alamitos, CA, 300-303.
    • KNAPP, D. W. 1990. Feedback-driven datapath optimization in Fasolt. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'90) IEEE Computer Society Press, Los Alamitos, CA, 300-303.
    • In Proceedings of the International Conference on Computer-Aided Design ICCAD'
  • 17
    • 0027001638 scopus 로고    scopus 로고
    • AND NESTOR, J. A. 1992. Data path allocation using an extended binding model
    • 29th ACM I IEEE Conference on Design Automation (DAC '92, Anaheim, CA, June 8-12), D. G. Schweikert, Ed. IEEE Computer Society Press, Los Alamitos, CA, 279-284.
    • KRISHNAMOORTHY, G. AND NESTOR, J. A. 1992. Data path allocation using an extended binding model. In Proceedings of the 29th ACM I IEEE Conference on Design Automation (DAC '92, Anaheim, CA, June 8-12), D. G. Schweikert, Ed. IEEE Computer Society Press, Los Alamitos, CA, 279-284.
    • In Proceedings of the
    • Krishnamoorthy, G.1
  • 18
    • 0023174393 scopus 로고    scopus 로고
    • AND PARKER, A. C. 1987. REAL: A program for REgister ALlocation
    • 24th ACM/IEEE Conference on Design Automation (DAC '87, Miami Beach, FL, June 28-July 1, 1987), A. O'Neill and D. Thomas, Eds. ACM Press, New York, NY, 210-215.
    • KURDAHI, F. J. AND PARKER, A. C. 1987. REAL: A program for REgister ALlocation. In Proceedings of the 24th ACM/IEEE Conference on Design Automation (DAC '87, Miami Beach, FL, June 28-July 1, 1987), A. O'Neill and D. Thomas, Eds. ACM Press, New York, NY, 210-215.
    • In Proceedings of the
    • Kurdahi, F.J.1
  • 20
    • 0025567579 scopus 로고    scopus 로고
    • ELWOOD, W. L., and GIRCZYC, E. F. 1990. a generalized interconnect model for data path synthesis
    • 90, Orlando, FL, June 24-28, R. C. Smith, Ed. ACM Press, New York, NY, 168-173.
    • LY, T. A., ELWOOD, W. L., AND GIRCZYC, E. F. 1990. A generalized interconnect model for data path synthesis. In Proceedings of the ACMI IEEE Conference on Design Automation (DAC '90, Orlando, FL, June 24-28), R. C. Smith, Ed. ACM Press, New York, NY, 168-173.
    • In Proceedings of the ACMI IEEE Conference on Design Automation DAC '
    • Arun, L.Y.T.1
  • 21
    • 0027561267 scopus 로고    scopus 로고
    • AND MOWCHENKO, J. 1993. Applying simulated evolution to high level synthesis
    • 12, 3 (Mar. 1993), 389-409.
    • LY, T. AND MOWCHENKO, J. 1993. Applying simulated evolution to high level synthesis. IEEE Trans. Comput.-Aided Des. 12, 3 (Mar. 1993), 389-409.
    • IEEE Trans. Comput.-Aided Des.
    • Tarni, L.Y.1
  • 22
    • 0025489298 scopus 로고    scopus 로고
    • AND KowALSKI, T. J. 1990. Incorporating bottom-up design into hardware synthesis
    • 9, 9 (Sept. 1990), 938-950.
    • McFARLAND, M. C. AND KowALSKI, T. J. 1990. Incorporating bottom-up design into hardware synthesis. IEEE Trans. Comput.-Aided Des. 9, 9 (Sept. 1990), 938-950.
    • IEEE Trans. Comput.-Aided Des.
    • McFarland, M.C.1
  • 23
    • 0025386057 scopus 로고    scopus 로고
    • AND PARKER, A. C. 1990. the high-level synthesis of digital systems
    • 78, 2 (Feb. 1990), 301-317.
    • McFARLAND, M. C. AND PARKER, A. C. 1990. The high-level synthesis of digital systems. IEEE Computer 78, 2 (Feb. 1990), 301-317.
    • IEEE Computer
    • McFarland, M.C.1
  • 24
    • 0000577173 scopus 로고    scopus 로고
    • AND KRISHNAMOORTHY, G. 1992. SALSA: A new approach to scheduling with timing constraints
    • 12, 8 (Aug.), 1107-1122.
    • NESTOR, J. A. AND KRISHNAMOORTHY, G. 1992. SALSA: A new approach to scheduling with timing constraints. IEEE Trans. Comput.-Aided Des. 12, 8 (Aug.), 1107-1122.
    • IEEE Trans. Comput.-Aided Des.
    • Nestor, J.A.1
  • 26
    • 0025546588 scopus 로고    scopus 로고
    • AND KONUK, H. 1990. a linear program driven scheduling and allocation method followed by an interconnect optimization algorithm
    • 90, Orlando, FL, June 24-28, R. C. Smith, Ed. ACM Press, New York, NY, 77-83.
    • PAPACHRISTOU, C. A. AND KONUK, H. 1990. A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm. In Proceedings of the ACM I IEEE Conference on Design Automation (DAC '90, Orlando, FL, June 24-28), R. C. Smith, Ed. ACM Press, New York, NY, 77-83.
    • In Proceedings of the ACM I IEEE Conference on Design Automation DAC '
    • Papachristou, C.A.1
  • 27
    • 0024682923 scopus 로고    scopus 로고
    • KNIGHT, J., and GIRZYC, E. 1986. HAL: A multi-paradigm approach to datapath synthesis
    • 1989. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. CAD 8, 6 (June 1989), 661-679.
    • PAULIN, P., KNIGHT, J., AND GIRZYC, E. 1986. HAL: A multi-paradigm approach to datapath synthesis. In Proceedings of the Conference on Design Automation PAULIN, P. G. AND KNIGHT, J. P. 1989. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. CAD 8, 6 (June 1989), 661-679.
    • In Proceedings of the Conference on Design Automation PAULIN, P. G. and KNIGHT, J. P.
    • Paulin, P.1
  • 29
    • 0026966664 scopus 로고    scopus 로고
    • KURDAHI, F. J., GAJSKI, D. D., Wu, A. C.-H., and CHAIYAKUL, V. 1992. Accurate layout area and delay modeling for system level design
    • (ICCAD '92, Santa Clara, CA, Nov. 8-12), L. Trevillyan, Ed. IEEE Computer Society Press, Los Alamitos, CA, 355-361.
    • RAMACHANDRAN, C., KURDAHI, F. J., GAJSKI, D. D., Wu, A. C.-H., AND CHAIYAKUL, V. 1992. Accurate layout area and delay modeling for system level design. In Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '92, Santa Clara, CA, Nov. 8-12), L. Trevillyan, Ed. IEEE Computer Society Press, Los Alamitos, CA, 355-361.
    • In Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design
    • Ramachandran, C.1
  • 30
    • 0028452826 scopus 로고    scopus 로고
    • MUJUMDAR, A., JAIN, R., and DE LEONE, R. 1994. Optimal and heuristic algorithms for solving the binding problem
    • 2, 2 (June 1994), 211-225.
    • RIM, M., MUJUMDAR, A., JAIN, R., AND DE LEONE, R. 1994. Optimal and heuristic algorithms for solving the binding problem. IEEE Trans. Very Large Scale Integr. Syst. 2, 2 (June 1994), 211-225.
    • IEEE Trans. Very Large Scale Integr. Syst.
    • Rim, M.1
  • 31
    • 0026925325 scopus 로고    scopus 로고
    • AND Hsu, Y. C. 1992. an automatic data path allocator
    • 11, 9 (Sep. 1992), 1053-1064.
    • TSAI, F. S. AND Hsu, Y. C. 1992. An automatic data path allocator. IEEE Trans. Comput.-Aided Des. 11, 9 (Sep. 1992), 1053-1064.
    • IEEE Trans. Comput.-Aided Des.
    • Tsai, F.S.1
  • 32
    • 0022756374 scopus 로고    scopus 로고
    • AND SIEWIOREK, D. P. 1986. Automated synthesis of data paths in digital systems
    • 5, 3 (July 1986), 379-395.
    • TSENG, C. AND SIEWIOREK, D. P. 1986. Automated synthesis of data paths in digital systems. IEEE Trans. Comput.-Aided Des. 5, 3 (July 1986), 379-395.
    • IEEE Trans. Comput.-Aided Des.
    • Tseng, C.1
  • 33
    • 0026175277 scopus 로고    scopus 로고
    • AND PARKER, A. C. 1991. 3D scheduling: High-level synthesis with floorplanning
    • (DAC '91, San Francisco, CA, June 17-21), A. R. Newton, Ed. ACM Press, New York, NY, 668-673.
    • WENG, J.-P. AND PARKER, A. C. 1991. 3D scheduling: High-level synthesis with floorplanning. In Proceedings of the 28th ACM I IEEE Conference on Design Automation (DAC '91, San Francisco, CA, June 17-21), A. R. Newton, Ed. ACM Press, New York, NY, 668-673.
    • In Proceedings of the 28th ACM I IEEE Conference on Design Automation
    • Weng, J.-P.1


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