Simultaneous scheduling, allocation and binding in high level synthesis

Electronics Letters

Volumn 33, Issue 18, 1997, Pages 1516-1518

  Kollig, P ^a   Al Hashimi, B M ^a  

^a STAFFORDSHIRE UNIVERSITY   (United Kingdom)

Author keywords

Circuit CAD; Digital circuits

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; RESOURCE ALLOCATION; SIMULATED ANNEALING;

HIGH LEVEL SYNTHESIS (HLS);

DIGITAL CIRCUITS;

EID: 0031211386     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19971039     Document Type: Article

References (6)

1. PAULIN, P.G., and KNIGHT, J.P.: 'Algorithms for high-level synthesis', IEEE Des. Test Comput., 1989, pp. 18-31
2. DEVADAS, S., and NEWTON, A.R.: 'Algorithms for hardware allocation in data path synthesis', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1989, 8, (7), pp. 768-781
3. DHODHI, M.K., HIELSCHER, F.H., STORER, R.H., and BHASKER, J.: 'Datapath synthesis using a problem-space genetic algorithm', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1995, 14, (8), pp. 934-944
4. LY, T.A., and MOWCHENKO, J.T.: 'Applying simulated evolution to high level synthesis', IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1993, 12, (3), pp. 389-409
5. DEKKERS, A., and AARTS, E.: 'Global optimisation and simulated annealing', Math. Program., 1991, 50, pp. 367-393
6. KOLLIG, P., AL-HASHIMI, B.M., and ABBOTT, K.M.: 'Efficient scheduling of behavioural descriptions in high-level synthesis', IEE Proc., Comput. Digit. Tech., 1997, 144, (2), pp. 75-82