High-level synthesis under multi-cycle interconnect delay

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 662-667

  Jeon, Jinhwan ^a   Kim, Daehong ^a   Shin, Dongwan ^b   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clocks; Computer architecture; Delay effects; Delay systems; Geometry; High level synthesis; Inductance; Logic; Noise generators; Scheduling algorithm

Indexed keywords

BINS; CLOCKS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; GEOMETRY; HIGH LEVEL SYNTHESIS; INDUCTANCE; NOISE GENERATORS; SCHEDULING; SCHEDULING ALGORITHMS; SYNTHESIS (CHEMICAL);

CRITICAL PATH LENGTHS; DELAY EFFECTS; DELAY SYSTEMS; DISTRIBUTED TARGET; INTERCONNECT DELAY; LOGIC; PROCESS TECHNOLOGIES; SCHEDULING AND BINDINGS;

DATA FLOW ANALYSIS;

EID: 84949817096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913385     Document Type: Conference Paper

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