Behavior-to-placed RTL synthesis with performance-driven placement

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 320-325

  Kim, Daehong ^a   Jung, Jinyong ^a   Lee, Sunghyun ^a   Jeon, Jinhwan ^b   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

^b GCT Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; DATA TRANSFER; LOGIC DESIGN;

DISTRIBUTED REGISTER ARCHITECTURES;

LOGIC CIRCUITS;

EID: 0035208967     PISSN: 10923152     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCAD.2001.968640     Document Type: Article

References (16)

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6. Parallel algorithm for simultaneous scheduling, binding and floorplanning in high-level synthesis
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8. A performance-driven macro-block placer for architectural evaluation of ASIC designs
9. High-level synthesis under multi-cycle interconnect delay
10. System clock estimation based on clock slack minimization
11. Performance-driven constructive placement
12. Backward-annotation of post layout delay information into high-level synthesis process for performance optimization