Efficient circuit clustering for area and power reduction in FPGAs

ACM Transactions on Design Automation of Electronic Systems

Volumn 7, Issue 4, 2002, Pages 643-663

  Singh, Amit ^a   Parthasarathy, Ganapathy ^b   Marek Sadowska, Malgorzata ^b  

^a XILINX INC   (United States)

^b University of California   (United States)

Author keywords

Clustering; Congestion; FPGA; Interconnect; Placement; Power; Rent

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUITS; LOGIC DESIGN; TRANSISTORS;

CIRCUIT CLUSTERING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036826796     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/605440.605448     Document Type: Article

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