Towards an ultra-low-power architecture using single-electron tunneling transistors

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 312-317

  Changyun, Zhu ^a   Zhenyu, Gu ^b   Li, Shang ^a   Dick, Robert P ^a   Knobel, Robert G ^a  

^a QUEEN S UNIVERSITY   (Canada)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

Low power; Nanoelectronics; Reconfigurable architecture; Single electron tunneling transistor (SET)

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC POWER UTILIZATION; ELECTRON TUNNELING; NANOELECTRONICS; TRANSISTORS;

RECONFIGURABLE ARCHITECTURE; SINGLE ELECTRON TUNNELING TRANSISTOR (SET); ULTRALOW-POWER DESIGNS;

INTEGRATED CIRCUIT LAYOUT;

EID: 34547240884     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375178     Document Type: Conference Paper

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