Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 39, Issue 4 B, 2000, Pages 2321-2324

  Uchida, Ken ^a   Matsuzawa, Kazuya ^a   Koga, Junji ^a   Ohba, Ryuji ^a   Takagi, Shin Ichi ^a   Toriumi, Akira ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Circuit simulation; Coulomb blockade; Device modeling; Master equation; Orthodox theory; SET; Single electron tunneling; SPICE

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; CORRELATION METHODS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRON TUNNELING; HYBRID INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

COULOMB BLOCKADE; ORTHODOX THEORY; SINGLE ELECTRON TRANSISTOR CIRCUITS; SOURCE TO DRAIN VOLTAGE; STEADY STATE MASTER EQUATION METHOD;

MOSFET DEVICES;

EID: 0033715104     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.39.2321     Document Type: Article

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