A quasi-analytical SET model for few electron circuit simulation

IEEE Electron Device Letters

Volumn 23, Issue 6, 2002, Pages 366-368

  Mahapatra, Santanu ^b   Ionescu, Adrian Mihai ^a,b   Banerjee, Kaustav ^a,c  

^a IEEE

^b EPFL   (Switzerland)

^c Stanford University   (United States)

Author keywords

Few electron circuit; Semiconductor device modeling; SET CMOS co simulation; Single electron transistor

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRON TUNNELING; LEAKAGE CURRENTS; LOGIC CIRCUITS; MONTE CARLO METHODS; THERMAL EFFECTS; TRANSCONDUCTANCE; TRANSISTORS;

DRAIN CURRENT; FEW ELECTRON CIRCUIT; HYBRID CIRCUIT; PARAMETER EXTRACTION; SINGLE ELECTRON TRANSISTOR;

SEMICONDUCTOR DEVICE MODELS;

EID: 0036609870     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.1004237     Document Type: Letter

References (11)

1. SIMON-A simulator for single-electron tunnel devices and circuits
2. A new logic family based on single-electron transistors
3. Macromodeling of single electron transistors for efficient circuit simulation
4. SPICE model for the single electron tunnel junction
5. Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits
6. Asynchronous analogue-to-digital converter for single-electron circuits
7. Single electron transistor with two gate inputs
8. Single electron pass transistor logic and its application to a binary adder
9. Single electron devices and their applications
10. Analytic I-V model for single-electron transistors