A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 497-502

  Mahapatra, Santanu ^a   Banerjee, Kaustav ^b   Pegeon, Florent ^c   Ionescu, Adrian Mihai ^a  

^a EPFL   (Switzerland)

^b University of California   (United States)

^c Silvaco Data Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COULOMB BLOCKADE; ELECTRIC POTENTIAL; GATES (TRANSISTOR); MANY VALUED LOGICS; MONTE CARLO METHODS;

HYBRID CIRCUITS; NEGATIVE DIFFERENTIAL RESISTANCE (NDR); SINGLE ELECTRON TRANSISTOR (SET) DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 0346778737     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159730     Document Type: Conference Paper

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