Interfacial layer dependence of HFSIXOy gate stacks on vT instability and charge trapping using ULTRA-short pulse I-V characterization

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 75-79

  Young, C D ^a   Choi, R ^a   Sim, J H ^a   Lee, B H ^b   Zeitzoff, P ^a   Zhao, Y ^c   Matthews, K ^a   Brown, G A ^a   Bersuker, G ^a  

^a SEMATECH   (United States)

^b IBM   (United States)

^c Keithley Instruments Inc   (United States)

Author keywords

Charge trapping; Hafnium; Interface layer; Pulse I V

Indexed keywords

CHARGE TRAPPING; GATE STACKS; INTERFACE LAYERS; PULSE I-V;

ELECTRIC CHARGE; ELECTRIC VARIABLES MEASUREMENT; ELECTRON TRAPS; HAFNIUM COMPOUNDS; INTERFACES (MATERIALS); TRANSIENTS; ULTRASHORT PULSES;

GATES (TRANSISTOR);

EID: 23844504847     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. R. Choi, S. Rhee, J. C. Lee, B. H. Lee, and G. Bersuker, "Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress," to be published in IEEE Electron Device Letters, March, vol. 26, 2005.
2. 2 dual layer gate dielectrics," IEEE Electron Device Letters, vol. 24, pp. 87, 2003.
3. 2 gate dielectrics," presented at 41st Annual IEEE Intl. Reliability Physics Symp. Proc., pp. 41, 2003.
4. L. Pantisano, E. Cartier, A. Kerber, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groeseneken, and H. E. Maes, "Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide," presented at Symp. on VLSI Technology Digest of Tech. Papers, pp. 163, 2003.
5. C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, Y. Kim, J. Gutt, P. Lysaght, J. Bennett, C. H. Lee, S. Gopalan, M. Gardner, P. M. Zeitzoff, G. Groeseneken, R. W. Murto, and H. R. Huff, "Charge Trapping and Mobility Degradation in MOCVD Hafnium Silicate Gate Dielectric Stack Structures," presented at 203rd Fall Meeting of the Electrochemical Society, Physics and Technology of High-K Gate Dielectrics - II, PV2003-22, pp. 347, 2003.
6. J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High-k dielectrics and MOSFET characteristics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, pp. 4.4.1, 2003.
7. C. D. Young, G. Bersuker, G. A. Brown, P. Lysaght, P. Zeitzoff, R. W. Murto, and H. R. Huff, "Charge trapping and device performance degradation in MOCVD hafnium-based gate dielectric stack structures," presented at 42nd Annual IEEE Intl. Reliability Physics Symp. Proc, pp. 597, 2004.
8. B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeitzoff, R. W. Murto, L. Larson, and C. Ramiller, "Intrinsic Characteristics of High-k Devices and Implications of Fast Transient Charging Effects (FTCE)," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, pp. 35.4.1, 2004.
9. C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, "Characterization and modeling of hysteresis phenomena in high K dielectrics," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, pp. 30.7.1, 2004.
10. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, "Effects of Preexisting Defects on Reliability Assessment of High-K Gate Dielectrics," Microelectronics Reliability, vol. 44, pp. 1509, 2004.
11. B. H. Lee, J. H. Sim, R. Choi, G. Bersuker, K. Matthew, N. Moumen, J. J. Peterson, and L. Larson, "Localized transient charging and it's implication on the hot carrier reliability of HfSiON MOSFETs," presented at 42nd Annual IEEE Intl. Reliability Physics Symp. Proc., pp. 691, 2004.
12. C. D. Young, Y. Zhao, M. Pendley, B. H. Lee, K. Matthews, J. H. Sim, R. Choi, G. A. Brown, R. W. Murto, and G. Bersuker, "Ultra-Short Pulse Current - Voltage Characterization of the Intrinsic Charactistics of High-k Devices," to be published in Japanese Journal of Applied Physics, vol. 44, No. 4B, 2005.
13. K. A. Jenkins, J. Y.-C. Sun, and J. Gautier, "Characteristics of SOI FETs under pulsed conditions," IEEE Transactions on Electron Devices, vol. 44, pp. 1923, 1997.
14. J. Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman, P. Majhi, J. J. Peterson, S. Gopalan, B. Foran, H.-J. Li, B. H. Lee, G. Bersuker, P. Zeitzoff, G. A. Brown, P. Lysaght, C. D. Young, R. W. Murto, and H. R. Huff, "Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface," presented at 2004 Spring Meeting of the Material Research Society, pp. E 1.4.1, 2004.
15. Y. Zhao, C. D. Young, M. Pendley, K. Matthews, B. H. Lee, and G. A. Brown, "Effective Minimization of Charge Trapping in High-k Gate Dielectrics with an Ultra-Short Pulse Technique," presented at Intl. Conf. on Solid State and Integrated Circuit Technology, pp. 407, 2004.
16. G. Bersuker, P. Zeitzoff, J. H. Sim, B. H. Lee, R. Choi, G. A. Brown, and C. D. Young, "Mobility Evaluation in High-K Devices," presented at IEEE Intl. Integrated Reliability Workshop Final Report, pp. 141, 2004.
17. G. Bersuker, J. H. Sim, C. D. Young, R. Choi, B. H. Lee, P. Lysaght, G. A. Brown, P. Zeitzoff, M. Gardner, R. W. Murto, and H. R. Huff, "Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance," presented at 2004 Spring Meeting of the Material Research Society, pp. 31, 2004.
18. J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Intl. Conf. on Characterization and Metrology for ULSI Technology, pp. 235, 1998.
19. G. Bersuker, P. Zeitzoff, J. Barnett, N. Moumen, B. Foran, C. D. Young, J. J. Peterson, and P. Lysaght, "Interface-Induced Mobility Degradation in High-k Transistors," Japanese Journal of Applied Physics, vol. 43, pp. 7899, 2004.