Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 7, 2007, Pages 1564-1572

  Chalvatzis, Theodoras ^a,b   Yau, Kenneth H K ^a,b   Aroca, Ricardo A ^a,b   Schvan, Peter ^a,c   Yang, Ming Ta ^d   Voinigescu, Sorin P ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c NORTEL NETWORKS   (Canada)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Decision circuit; Flip flop; GP CMOS; LP CMOS; MOS CML; Retimer; Transimpedance amplifier

Indexed keywords

DECISION CIRCUITS; GP CMOS; LP CMOS; MOS-CML; RETIMERS; TRANSIMPEDANCE AMPLIFIERS;

BROADBAND AMPLIFIERS; ELECTRIC INVERTERS; FLIP FLOP CIRCUITS; JITTER; MOSFET DEVICES; TOPOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 34347245193     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.899093     Document Type: Conference Paper

References (21)

1. S. Sidiropoulos, N. Acharya, C. Pak, J. D. A. Feldman, L. Haw-Jyh, M. Loinaz, R. S. Narayanaswami, C. Portmann, S. Rabii, A. Salleh, S. Sheth, L. Thon, K. Vleugels, P. Yue, and D. Stark, "An 800 mW 10 Gb Ethernet transceiver in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 168-169.
2. B.-J. Lee, M.-S. Hwang, S.-H. Lee, and D.-K. Jeong, "A 2.5-10 Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 76-77.
3. C. Kromer, G. Sialm, C. Berger, T. Morf, M. L. Schmatz, F. Ellinger, D. Erni, G.-L. Bona, and H. Jackel, "A 100-mW 4 × 10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2667-2679, Dec. 2005.
4. J. Kim, J.-K. Kim, B.-J. Lee, M.-S. Hwang, H.-R. Lee, S.-H. Lee, N. Kim, D.-K. Jeong, and W. Kim, "Circuit techniques for a 40 Gb/s transmitter in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 150-151.
5. T. O. Dickson and S. P. Voinigescu, "Low-power circuits for a 10.7-to-86 Gb/s 80-Gb/s serial transmitter in 130-nm SiGe BiCMOS," in IEEE Compound Semiconductor IC Symp. (CSICS) Tech. Dig., 2006, pp. 235-238.
6. T. Suzuki, T. Takahashi, T. Hirose, and M. Takikawa, "A 80-Gbit/s D-type flip-flop circuit using InP HEMT technology," IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1706-1711, Oct. 2004.
7. Y. Amamiya, Z. Yamazaki, Y. Suzuki, M. Mamada, and H. Hida, "Low supply voltage operation of over-40-Gb/s digital ICs on Parallel-Current- Switching latch circuitry," IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2111-2117, Oct. 2005.
8. M. Meghelli, "A 43-Gb/s full-rate clock transmitter in 0.18μm SiGe BiCMOS technology "IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2046-2050, Oct. 2005.
9. T. O. Dickson, R. Beerkens, and S. P. Voinigescu, "A 2.5-V, 45-Gb/s decision circuit using SiGe BiCMOS logic," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 994-1003, Apr. 2005.
10. K. Kanda, D. Yamazaki, T. Yamamoto, M. Horinaka, J. Ogawa, H. Tamura, and H. Onodera, "A 40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm standard CMOS," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 152-290.
11. D. Kehrer and H.-D. Wohlmuth, "A 60-Gb/s 0.7-V 10-mW monolithic transformer-coupled 2:1 multiplexer in 90 nm CMOS," in IEEE Compound Semiconductor IC Symp. (CSICS) Tech. Dig., 2004, pp. 105-108.
12. T. O. Dickson, K. H. K. Yau, T. Chalvatzis, A. M. Mangan, E. Laskin, R. Beerkens, P. Westergaard, M. Tazlauanu, M. T. Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1830-1845, Aug. 2006.
13. C. Kromer, G. Sialm, T. Morf, M. L. Schmatz, F. Ellinger, D. Erni, and H. Jackel, "A low-power 20-GHz 52-dB transimpedance amplifier in 80-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885-894, Jun. 2004.
14. T. Chalvatzis and S. P. Voinigescu, "A low-noise 40-GS/s continuoustime bandpass ΔΣ ADC centered at 2 GHz," in Radio Frequency Integrated Circuits (RFIC) Symp. Tech. Dig., 2006, pp. 323-326.
15. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004, ch. 9.
16. S. P. Voinigescu, T. O. Dickson, T. Chalvatzis, A. Hazneci, E. Laskin, R. Beerkens, and I. Khalid, "Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes," in Proc. IEEE Custom Integrated Circutis (CICC) Conf., 2005, pp. 111-118.
17. F. Pera and S. P. Voinigescu, "An SOI CMOS, high gain and low noise transimpedance-limiting amplifier for 10 Gb/s applications," in Radio Frequency Integrated Circuits (RFIC) Symp. Tech. Dig., 2006, pp. 401-404.
18. T. Chalvatzis, K. H. K. Yau, P. Schvan, M.-T. Yang, and S. P. Voinigescu, "A 40-Gb/s decision circuit in 90-nm CMOS," in Proc. European Solid-State Circuits (ESSCIRC) Conf., 2006, pp. 515-518.
19. W. M. Huang, H. S. Bennett, J. Costa, P. Cottrell, A. A. Immorlica, J.-E. Mueller, M. Racanelli, H. Shichijo, C. E. Weitzel, and B. Zhao, "RF, analog and mixed signal technologies for communication ICs - An ITRS perspective," in IEEE Bipolar/BiCMOS Circuits Technology Meeting (BCTM) Tech. Dig., 2006, pp. 65-71.
20. S. P. Voinigescu, S. T. Nicolson, M. Khanpour-Ardestani, K. K. W. Tang, K. H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, and M.-T. Yang, "CMOS SoCs at 100 GHz: System architectures, device characterization, and IC design infrastructure," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007.
21. C.-F. Liao and S.-I. Liu, "A 40 Gb/s transimpedance-AGC amplifier with 19 dB DR in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 54-55.