A 2.5 - 10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Lee, Bong Joon ^a   Hwang, Moon Sang ^a   Lee, Sang Hyun ^b   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; JITTER; TIMING CIRCUITS;

BINARY PHASE DETECTOR; CLOCK AND DATA RECOVERY CIRCUITS; DETERMINISTIC JITTER; RANDOM JITTER;

TRANSCEIVERS;

EID: 0038306651     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Fiedler, et al., "A 1.0625Gb/s Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis," ISSCC Digest of Technical Papers, pp. 238-239, Feb. 1997
2. Y. Moon, et al., "A 0.6 - 2.5Gbaud CMOS Tracked 3× Oversampling Transceiver with Dead Zone Phase Detection for Robust Clock/Data Recovery," ISSCC Digest of Technical Papers, pp. 212-213, Feb. 2001
3. S. Lee, et al., "A 5Gb/s 0.25mm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit," ISSCC Digest of Technical Papers, pp. 256-257, Feb. 2002