An 800mW 10Gb ethernet transceiver in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Sidiropoulos, Stefanos ^a   Acharya, Nikhil ^a   Chau, Pak ^a   Dao, Joseph ^a   Feldman, Arnold ^a   Liaw, Haw Jyh ^a   Loinaz, Marc ^a   Sekhar Narayanaswami, R ^a   Portmann, Clemenz ^a   Rabii, Shahriar ^a   Salleh, Azmeer ^a   Sheth, Siddharth ^a   Thon, Lars ^a   Vleugels, Katelijn ^a   Yue, Patrick ^a   Stark, Don ^a  

^a Aeluros Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DIAGRAMS; ETHERNET PACKETS; PACKET CODING;

COMMUNICATION SYSTEMS; ENCODING (SYMBOLS); MULTIPLEXING; PACKET NETWORKS; SEMICONDUCTOR DEVICES; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 2442651367     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. "CSMA/CD Access Method, PHY Specification, MAC, PHY, and Management Parameters for 10Gb/s," IEEE 802.3-ae, 2002.
2. SFI-4 Phase 2 (00-192 4-bit SERBES to Framer Interface), Optical Internetworking Forum, OIF-SF14-02.0, Sept. 2002.
3. S. Sidiropoulos and M. Horowitz, "A Semi-Digital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
4. K.C. Tsai and P. Gray, "A 1-W CMOS Class-E Power Amplifier for Wireless Communications," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 962-970, July 1999.