A 40-Gb/s decision circuit in 90-nm CMOS

ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Volumn , Issue , 2006, Pages 512-515

  Chalvatzis, T ^a   Yau, K H K ^a   Schvant, P ^b   Yang, M T ^c   Voinigescu, S P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b NORTEL NETWORKS   (Canada)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Decision circuit; MOS CML; Retiming D flip flop

Indexed keywords

DECISION CIRCUIT; FULL-RATE RETIMING; JITTER REDUCTION; MASTER-SLAVE LATCH TOPOLOGY;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ENERGY DISSIPATION; MOS DEVICES; MOSFET DEVICES;

NETWORKS (CIRCUITS);

EID: 39549095731     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2006.307502     Document Type: Conference Paper

References (9)