A fast hardware/software co-verification method for System-On-a-Chip by using a C/C++ simulator and FPGA emulator with shared register communication

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 299-304

  Nakamura, Yuichi ^a   Hosokawa, Kouhei ^a   Kuroda, Ichiro ^a   Yoshikawa, Ko ^a   Yoshimura, Takeshi ^b  

^a NEC CORPORATION   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

Co Verification; FPGA Emulation

Indexed keywords

CODES (STANDARDS); COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; MACHINE DESIGN; PROJECT MANAGEMENT;

CO-VERIFICATION; FPGA EMULATION; SHARED COMMUNICATION REGISTER (SCR);

SYSTEMS ANALYSIS;

EID: 4444379641     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996655     Document Type: Conference Paper

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