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Volumn , Issue , 2004, Pages 96-102

Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; NETWORK PROTOCOLS; RAPID PROTOTYPING;

EID: 4944260876     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (12)
  • 3
    • 0034853865 scopus 로고    scopus 로고
    • A transaction-based unifi ed simulation/emulation architecture for functional verifi Cation
    • Las Vegas, USA
    • M. Kudlugi, S. Hassoun, C. Selvidge, D. Pryor, "A Transaction-based Unifi ed Simulation/Emulation Architecture for Functional Verifi cation". In Proceedings of Design Automation Conference, Las Vegas, USA, 2001, pages 623-628.
    • (2001) Proceedings of Design Automation Conference , pp. 623-628
    • Kudlugi, M.1    Hassoun, S.2    Selvidge, C.3    Pryor, D.4
  • 7
    • 4944259981 scopus 로고    scopus 로고
    • The SCE-API 1.0 Standard
    • The SCE-API 1.0 Standard, http://www.eda.org/itc/
  • 8
    • 4944220818 scopus 로고    scopus 로고
    • SynaptiCAD Inc., SimuTag, http://www.syncad.com/
    • SimuTag
  • 9
    • 67249088989 scopus 로고    scopus 로고
    • Xilinx Inc., ChipScope Pro, http://www.xilinx.com/
    • ChipScope Pro
  • 10
    • 84855602682 scopus 로고    scopus 로고
    • Altera Corp., SignalTap II, http://www.altera.com/
    • SignalTap II
  • 12
    • 84962381667 scopus 로고    scopus 로고
    • OPENCORES.ORG, AES Project, http://www.opencores.org/
    • AES Project


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.