Component-based methodology for hardware design of a dataflow processing network

Proceedings - Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005

Volumn 2005, Issue , 2005, Pages 289-294

  Grou Szabo, Robert ^a   Ghattas, Hany ^a   Savaria, Yvon ^a   Nicolescu, Gabriela ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA PROCESSING; NAND CIRCUITS; NETWORK PROTOCOLS;

DATA-FLOW ARCHITECTURES; HARDWARE DESIGN; NAND GATES; VCI PROTOCOLS;

DATA FLOW ANALYSIS;

EID: 33748898481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2005.46     Document Type: Conference Paper

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