-
1
-
-
0033116422
-
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
-
April
-
V. Stojanovic and V. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems", IEEE JSSC, vol. 34, (no. 4), April 1999. p. 536-48.
-
(1999)
IEEE JSSC
, vol.34
, Issue.4
, pp. 536-548
-
-
Stojanovic, V.1
Oklobdzija, V.2
-
2
-
-
0142227166
-
Optimization of scannable latches for low energy
-
Oct.
-
V. Zyuban, "Optimization of scannable latches for low energy", IEEE Transactions on VLSI, Vol.11, Issue 5, Oct. 2003 Page(s):778-788
-
(2003)
IEEE Transactions on VLSI
, vol.11
, Issue.5
, pp. 778-788
-
-
Zyuban, V.1
-
3
-
-
0346715478
-
-
January, Wiley-IEEE Press
-
V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, N. M. Nedovic, "Digital System Clocking", January 2003, Wiley-IEEE Press
-
(2003)
Digital System Clocking
-
-
Oklobdzija, V.G.1
Stojanovic, V.M.2
Markovic, D.M.3
Nedovic, N.M.4
-
4
-
-
84941147323
-
-
"FLIP-FLOP" US Patent No. 6,232,810, Issued: 05/15
-
V. Stojanovic, V. G. Oklobdzija, "FLIP-FLOP" US Patent No. 6,232,810, Issued: 05/15/2001
-
(2001)
-
-
Stojanovic, V.1
Oklobdzija, V.G.2
-
5
-
-
0002516681
-
Sense amplifier-based flip-flop
-
San Francisco, February
-
B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung, "Sense Amplifier-Based Flip-Flop", 1999 IEEE ISSCC, San Francisco, February 1999.
-
(1999)
1999 IEEE ISSCC
-
-
Nikolic, B.1
Stojanovic, V.2
Oklobdzija, V.G.3
Jia, W.4
Chiu, J.5
Leung, M.6
-
6
-
-
16544381009
-
A clock skew absorbing flip-flop
-
San Francisco, Feb.
-
N. Nedovic, V. G. Oklobdzija, W. W. Walker, "A Clock Skew Absorbing Flip-Flop", 2003 IEEE ISSCC, San Francisco, Feb. 2003.
-
(2003)
2003 IEEE ISSCC
-
-
Nedovic, N.1
Oklobdzija, V.G.2
Walker, W.W.3
-
7
-
-
0034870298
-
Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance micro-processors
-
2001. 6-7 Aug.
-
J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, V. De, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance micro-processors", ISLPED, 2001. 6-7 Aug. 2001 Page(s):147-152
-
(2001)
ISLPED
, pp. 147-152
-
-
Tschanz, J.1
Narendra, S.2
Chen, Z.3
Borkar, S.4
Sachdev, M.5
De, V.6
-
9
-
-
0031640603
-
Semi-dynamic and dynamic flip-flops with embedded logic
-
F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," Symposium on VLSI Circuits, p.108-109, 1998
-
(1998)
Symposium on VLSI Circuits
, pp. 108-109
-
-
Klass, F.1
-
10
-
-
0028733872
-
A 2.2W, 80MHz superscalar RISC microprocessor
-
Dec.
-
G. Gerosa, S. Gary, C. Dietz, P. Dac, K. Hoover, J. Alvarez, "A 2.2W, 80MHz Superscalar RISC Microprocessor," IEEE JSSC, vol. 29, pp. 1440-1452, Dec. 1994.
-
(1994)
IEEE JSSC
, vol.29
, pp. 1440-1452
-
-
Gerosa, G.1
Gary, S.2
Dietz, C.3
Dac, P.4
Hoover, K.5
Alvarez, J.6
-
11
-
-
0028733304
-
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifier pipeline flip-flop scheme
-
Dec.
-
M. Matsui, H. Hara, Y. Uetani, K. Lee-Sup, T. Nagamatsu, Y.Watanabe, "A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifier pipeline flip-flop scheme," IEEE JSSC, vol. 29, pp. 1482-1491, Dec. 1994,
-
(1994)
IEEE JSSC
, vol.29
, pp. 1482-1491
-
-
Matsui, M.1
Hara, H.2
Uetani, Y.3
Lee-Sup, K.4
Nagamatsu, T.5
Watanabe, Y.6
-
12
-
-
35248867366
-
The stanford digital library metadata architecture
-
Baldonado, M., Chang, C.-C.K., Gravano, L., Paepcke, A.: The Stanford Digital Library Metadata Architecture. Int. J. Digit. Libr. 1 (1997) 108-121.
-
(1997)
Int. J. Digit. Libr.
, vol.1
, pp. 108-121
-
-
Baldonado, M.1
Chang, C.-C.K.2
Gravano, L.3
Paepcke, A.4
-
13
-
-
84886702569
-
A new method for design of robust digital circuits
-
21-23 March
-
D. Patil, S. Yun, S.-J. Kim, A. Cheung, M. Horowitz, S. Boyd, "A new method for design of robust digital circuits", Sixth International Symposium on Quality of Electronic Design, 2005, ISQED 2005. 21-23 March 2005 Page(s):676-681.
-
(2005)
Sixth International Symposium on Quality of Electronic Design, 2005, ISQED 2005
, pp. 676-681
-
-
Patil, D.1
Yun, S.2
Kim, S.-J.3
Cheung, A.4
Horowitz, M.5
Boyd, S.6
-
14
-
-
84941150877
-
-
"Transmission-gate based flip-flop" US Patent 6,642,765, Nov.
-
D. Markovic, J. Tschanz, V. De, "Transmission-gate based flip-flop" US Patent 6,642,765, Nov. 2003.
-
(2003)
-
-
Markovic, D.1
Tschanz, J.2
De, V.3
-
15
-
-
0034878683
-
Analysis of clocked timing elements for DVS effects over process parameter variation
-
Huntington Beach, California, August 6-7
-
H. Dao, K. Nowka, V. Oklobdzija, "Analysis of Clocked Timing Elements for DVS Effects over Process Parameter Variation", Proceedings of the International Symposium on Low Power Electronics and Design, Huntington Beach, California, August 6-7, 2001.
-
(2001)
Proceedings of the International Symposium on Low Power Electronics and Design
-
-
Dao, H.1
Nowka, K.2
Oklobdzija, V.3
-
16
-
-
33645000007
-
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
-
Feb.
-
H. Dao, B. Zeydel, V. Oklobdzija, "Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling" IEEE Transactions on VLSI, Volume 14, Issue 2, Feb. 2006 Page(s):122-134.
-
(2006)
IEEE Transactions on VLSI
, vol.14
, Issue.2
, pp. 122-134
-
-
Dao, H.1
Zeydel, B.2
Oklobdzija, V.3
|