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Volumn 4148 LNCS, Issue , 2006, Pages 360-369

Energy-delay space analysis for clocked storage elements under process variations

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; DELAY CIRCUITS; ENERGY EFFICIENCY; ENERGY STORAGE; TOPOLOGY;

EID: 33750046935     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11847083_35     Document Type: Conference Paper
Times cited : (3)

References (16)
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  • 4
    • 84941147323 scopus 로고    scopus 로고
    • "FLIP-FLOP" US Patent No. 6,232,810, Issued: 05/15
    • V. Stojanovic, V. G. Oklobdzija, "FLIP-FLOP" US Patent No. 6,232,810, Issued: 05/15/2001
    • (2001)
    • Stojanovic, V.1    Oklobdzija, V.G.2
  • 7
    • 0034870298 scopus 로고    scopus 로고
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    • 2001. 6-7 Aug.
    • J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, V. De, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance micro-processors", ISLPED, 2001. 6-7 Aug. 2001 Page(s):147-152
    • (2001) ISLPED , pp. 147-152
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  • 9
    • 0031640603 scopus 로고    scopus 로고
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    • F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," Symposium on VLSI Circuits, p.108-109, 1998
    • (1998) Symposium on VLSI Circuits , pp. 108-109
    • Klass, F.1
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    • A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifier pipeline flip-flop scheme
    • Dec.
    • M. Matsui, H. Hara, Y. Uetani, K. Lee-Sup, T. Nagamatsu, Y.Watanabe, "A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifier pipeline flip-flop scheme," IEEE JSSC, vol. 29, pp. 1482-1491, Dec. 1994,
    • (1994) IEEE JSSC , vol.29 , pp. 1482-1491
    • Matsui, M.1    Hara, H.2    Uetani, Y.3    Lee-Sup, K.4    Nagamatsu, T.5    Watanabe, Y.6
  • 14
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    • "Transmission-gate based flip-flop" US Patent 6,642,765, Nov.
    • D. Markovic, J. Tschanz, V. De, "Transmission-gate based flip-flop" US Patent 6,642,765, Nov. 2003.
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    • Feb.
    • H. Dao, B. Zeydel, V. Oklobdzija, "Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling" IEEE Transactions on VLSI, Volume 14, Issue 2, Feb. 2006 Page(s):122-134.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.