The WaveScalar architecture

ACM Transactions on Computer Systems

Volumn 25, Issue 2, 2007, Pages

  Swanson, Steven ^a,b   Schwerin, Andrew ^a,b   Mercaldi, Martha ^a,b   Petersen, Andrew ^a,b   Putnam, Andrew ^a,b   Michelson, Ken ^a,b   Oskin, Mark ^a,b   Eggers, Susan J ^a,b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b University of Washington   (United States)

Author keywords

Dataflow computing; Multithreading; WaveScalar

Indexed keywords

DATAFLOW COMPUTING; MULTITHREADING; PROCESSING ELEMENTS; WAVESCALAR;

BROADCASTING; DATA FLOW ANALYSIS; PROGRAM PROCESSORS; SEMANTICS; SILICON; TRANSISTORS;

COMPUTER ARCHITECTURE;

EID: 34249721013     PISSN: 07342071     EISSN: 15577333     Source Type: Journal    
DOI: 10.1145/1233307.1233308     Document Type: Article

References (54)

1. ADVE, S. V. AND GHARACHORLOO, K. 1996. Shared memory consistency models: A tutorial. Cornput. 29, 12, 66-76.
2. AGARWAL, V., HRISHIKESH, M. S., KECKLER, S. W., AND BURGER, D. 2000. Clock rate versus IPC: The end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 248-259.
3. ARVIND. 2005. Dataflow: Passing the token. ISCA keynote in Annual International Symposium on Computer Architecture.
4. ARVIND, NIKHIL, R. S., AND PINGALI, K. K. 1989. I-structures: Data structures for parallel computing. ACM Trans. Program. Lang. Syst. 11, 4, 598-632.
5. BARROSO, L. A., GHARACHORLOO, K., MCNAMARA, R., NOWATZYK, A., QADEER, S., SANO, B., SMITH, S., STETS, R., AND VERGHESE, B. 2000. Piranha: A scalable architecture based on single-chip multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 282-293.
6. BARTH, P. S., NIKHIL, R. S., AND ARVIND. 1991. M-structures: Extending a parallel, non-strict, functional languages with state. Tech. Rep. MIT/LCS/TR-327, Massachusetts Institute of Technology. March.
7. BECK, M., JOHNSON, R., AND PINGALI, K. 1991. From control flow to data flow. J. Parallel Distrib. Comput. 12, 2, 118-129.
8. BUDIU, M., VENKATARAMANI, G., CHELCEA, T, AND GOLDSTEIN, S. C. 2004. Spatial computation. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM Press, New York. 14-26.
9. CADENCE. 2007. Cadence website. http://www.cadence.com.
10. CHRYSOS, G. Z. AND EMER, J. S. 1998. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Los Alamitos, CA. 142-153.
11. CULLER, D. E. 1990. Managing parallelism and resources in scientific dataflow programs. Ph.D. thesis, Massachusetts Institute of Technology.
12. CULLER, D. E., SAH, A., SCHAUSER, K. E., VON EICKEN, T, AND WAWRZYNEK, J. 1991. FineGrain parallelism with minimal hardware support: A compiler-controlled threaded abstract machine. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM Press, New York. 164-175.
13. CYTRON, R., FERRANTE, J., ROSEN, B. K., WEGMAN, M. N., AND ZADECK, F. K. 1991. Efficiently computing static single assignment form and the control dependence graph. ACM Trans. Program. Lang. Syst. 13, 4, 451-490.
14. DALLY, W. J. AND SEITZ, C. L. 1987. Deadlock-Free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36, 5, 547-553.
15. DAVIS, A. L. 1978. The architecture and system method of DDM1: A recursively structured data driven machine. In Proceedings of the 5th Annual Symposium on Computer Architecture (ISCA). ACM Press, New York. 210-215.
16. DENNIS, J. B. AND MISUNAS, D. P. 1975. A preliminary architecture for a basic data-flow processor. In Proceedings of the 2nd Annual Symposium on Computer Architecture (ISCA). ACM Press, New York. 126-182.
17. DESIKAN, R., BURGER, D. C., KECKLER, S. W., AND AUSTIN, T. M. 2001. Sim-Alpha: A validated, execution-driven Alpha 21264 simulator. Tech. Rep. TR-01-23, University of Texas-Austin, Department of Computer Sciences.
18. EKMAN, M. AND STENSTRÖM, P. 2003. Performance and power impact of issue width in chip-multiprocessor cores. In Proceedings of the International Conference on Parallel Processing.
19. FEO, J. T., MILLER, P. J., AND SKEDZIELEWSKI, S. K. 1995. SISAL90. In Proceedings of the Conference on High Performance Functional Computing.
20. GOLDSTEIN, S. C. AND BUDIU, M. 2001. NanoFabrics: Spatial computing using molecular electronics. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 178-191.
21. GOODMAN, J. R., VERNON, M. K., AND WOEST, P. J. 1989. Efficient synchronization primitives for large-scale cache-coherent multiprocessors. In Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), ACM Press, New York. 64-75.
22. GRAFE, V. G., DAVIDSON, G. S., HOCH, J. E., AND HOLMES, V. P. 1989. The Epsilon dataflow processor. In Proceedings of the 16th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 36-45.
23. GURD, J. R., KIRKHAM, C. C., AND WATSON, I. 1985. The Manchester prototype dataflow computer. Commun. ACM 28, 1, 34-52.
24. HAMMOND, L., HUBBERT, B. A., SIU, M., PRABHU, M. K., CHEN, M., AND OLUKOTUN, K. 2000. The Stanford Hydra cmp. IEEE Micro. 20, 2, 71-84.
25. HRISHIKESH, M. S., BURGER, D., JOUPPI, N. P., KECKLER, S. W., FARKAS, K. I., AND SHIVAKUMAR, P. 2002. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Los Alamitos, CA. 14-24.
26. JAIN, A. E. A. 2001. A 1.2GHz Alpha microprocessor with 44.8GB/S chip pin bandwidth. In Proceedings of the IEEE International Solid-State Circuits Conference. Vol. 1. 240-241.
27. KECKLER, S. W., DALLY, W. J., MASKIT, D., CARTER, N. P., CHANG, A., AND LEE, W. S. 1998. Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Los Alamitos, CA. 306-317.
28. KISHI, M., YASUHARA, H., AND KAWAMURA, Y. 1983. Dddp-A distributed data driven processor. In Proceedings of the 10th Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society Press, Los Alamitos, CA. 236-242.
29. KREWEL, K. 2005. Alpha EV7 processor: A high-performance tradition continues. Microprocessor Rep.
30. LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th International Symposium on Microarchitecture (MICRO). 330-335.
31. LEE, W., BARUA, R., FRANK, M., SRIKRISHNA, D., BABB, J., SARKAH, V., AND AMARASINGHE, S. 1998. Space-Time scheduling of instruction-level parallelism on a Raw machine. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM Press, New York. 46-57.
32. LO, J. L., EMER, J. S., LEVY, H. M., STAMM, R. L., TULLSEN, D. M., AND EGGERS, S. J. 1997. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading. ACM Trans. Comput. Syst. 15, 3, 322-354.
33. MAHLKE, S. A., LIN, D. C., CHEN, W. Y., HANK, R. E., AND BRINGMANN, R. A. 1992. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO). IEEE Computer Society Press, Los Alamitos, CA. 45-54.
34. MAI, K., PAASKE, T., JAYASENA, N., Ho, R., DALLY, W. J., AND HOROWITZ, M. 2000. Smart memories: A modular reconfigurable architecture. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 161-171.
35. MERCALDI, M., SWANSON, S., PETERSEN, A., PUTNAM, A., SCHWERIN, A., OSKIN, M., AND EGGERS, S. J. 2006a. Instruction scheduling for a tiled dataflow architecture. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 141-150.
36. MERCALDI, M., SWANSON, S., PETERSEN, A., PUTNAM, A., SCHWERIN, A., OSKIN, M., AND EGGERS, S. J. 2006b. Modeling instruction placement on a spatial architecture. In Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures (SPAA). 158-169.
37. MUKHERJEE, S. S., WEAVER, C., EMER, J., REINHARDT, S. K., AND AUSTIN, T. 2008. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE Computer Society, Los Alamitos, CA. 29.
38. NAGARAJAN, R., SANKARALINGAM, K., BURGER, D., AND KECKLER, S. W. 2001. A design space evaluation of grid processor architectures. In Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO). IEEE Computer Society, Los Alamitos, CA. 40-51.
39. NICHOLS, B., BUTTLAR, D., AND FARRELL, J. P. 1996. Pthreads Programming. O'Reilly, Sebastopol, CA.
40. NIKHIL, R. 1990. The parallel programming language id and its compilation for parallel machines. In Proceedings of the Workshop on Massive Paralleism: Hardware, Programming and Applications. Acamedic Press.
41. PAPADOPOULOS, G. M. AND CULLER, D. E. 1990. Monsoon: An explicit token-store architecture. In Proceedings of the 17th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 82-91.
42. PAPADOPOULOS, G. M. AND TRAUB, K. R. 1991. Multithreading: A revisionist view of dataflow architectures. In Proceedings of the 18th Annual International Symposium on Computer Architecture (ISCA). ACM Press, New York. 342-351.
43. PETEHSEN, A., PUTNAM, A., MERCALDI, M., SCHWERIN, A., EGGERS, S., SWANSON, S., AND OSKIN, M. 2006. Reducing control overhead in dataflow architectures. In Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT). 182-191.
44. SANKARALINGAM, K., NAGARAJAN, R., LIU, H., KIM, C., HUH, J., BURGER, D., KECKLER, S. W., AND MOORE, C. R. 2003. Exploitingilp, tip, and dip with the polymorphous trips architecture, In. Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA). 422-433.
45. SHIMADA, T., HIRAKI, K., AND NISHIDA, K. 1984. An architecture of a data flow machine and its evaluation. ACM SIGARCH Comput. Architecure News 14, 2, 226-234.
46. SHIMADA, T., HIRAKI, K., NISHIDA, K., AND SEKIGUCHI, S. 1986. Evaluation of a prototype data flow processor of the sigma-1 for scientific computations. In Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society Press, Los Alamitos, CA. 226-234.
47. SMITH, A., GIBSON, J., MAHER, B., NETHERCOTE, N., YODER, B., BURGER, D., MCKINLE, K. S., AND BURRILL, J. 2006. Compiling for edge architectures. In Proceedings of the International Symposium on Code Generation and Optimization (CGO). IEEE Computer Society, Los Alamitos, CA. 185-195.
48. SPEC. 2000. SPEC CPU 2000 benchmark specifications. SPEC2000 Benchmark Release.
49. SWANSON, S. 2006. The WaveScalar architecture. Ph.D. thesis, University of Washington.
50. SWANSON, S., MICHELSON, K., SCHWERIN, A., AND OSKIN, M. 2003. Wavescalar. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE Computer Society, Los Alamitos, CA. 291.
51. SWANSON, S., PUTNAM, A., MERCALDI, M., MICHELSON, K., PETERSEN, A., SCHWERIN, A., OSKIN, M., AND EGGERS, S. J. 2006. Area-Performance trade-offs in tiled dataflow architectures. In Proceedings of the 33rd International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Los Alamitos, CA. 314-326.
52. TAYLOR, M. B., LEE, W., MILLER, J., WENTZLAFF, D., BRATT, I., GREENWALD, B., HOFFMANN, H., JOHNSON, P., KIM, J., PSOTA, J., SARAF, A., SHNIDMAN, N, STRUMPEN, V., FRANK, M., AMARASINGHE, S., AND AGARWAL, A. 2004. Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Los Alamitos, CA. 2.
53. TSMC. 2007. Silicon design chain cooperation enables nanometer chip design. Cadence Whitepaper. http://www.cadence.com/whitepapers/.
54. TULLSEN, D. M., LO, J. L., EGGERS, S. J., AND LEVY, H. M. 1999. Supporting fine-grained synchronization on a simultaneous multithreading processor. In Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA). IEEE Computer Society, Los Alamitos, CA. 54.