Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 1998, Pages 306-317

  Keckler, Stephen W ^a   Dally, William J ^a   Maskit, Daniel ^a   Carter, Nicholas P ^a   Chang, Andrew ^a   Lee, Whay S ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS; COMPUTER SOFTWARE; PROGRAM PROCESSORS;

COARSE THREAD PARALLELISM; INSTRUCTION LEVEL PARALLELISM; SUPERSCALAR PROCESSOR;

PROGRAM PROCESSORS; PARALLEL PROCESSING SYSTEMS;

EID: 0031593999     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)