Misalignment-tolerated, Cu Dual Damascene Interconnects with Low-k SiOCH film by a Novel Via-first, Multi-Hard-Mask Process for sub-100nm-node, ASICs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 853-856

  Ohtake, H ^a   Tagami, M ^a   Arita, K ^b   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIELECTRIC FILMS; ELECTRIC CONNECTORS; FABRICATION; PHOTORESISTS; RELIABILITY; SILICA;

DUAL DAMASCENE INTERCONNECTS (DDI);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0842266519     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. H. Ohtake, et. al., IEDM Tech. (2002) p599
2. R. Kanamura, et. al., VLSI Tech. (2003) p107,
3. A. Kajita, et. al., IITC Tech. (2003) p9.