Comprehensive process design for low-cost chip packaging with Circuit-under-pad (CUP) strucure in porous-SiOCH film

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 12-14

  Tagami, M ^a   Ohtake, H ^a   Abe, M ^a   Ito, F ^a   Takeuchi, T ^a   Ohto, K ^b   Usami, T ^b   Suzuki, M ^b   Suzuki, T ^c   Sashida, N ^c   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c Sumitomo Bakelite Co Ltd ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; MOLDING; OPTIMIZATION; SILICON COMPOUNDS; SILICON WAFERS;

CIRCUIT-UNDER-PAD (CUP); INTERCONNECT TECHNOLOGY; STRIP PROCESSES;

LARGE SCALE SYSTEMS;

EID: 28244485434     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Ueki et al., Proc. of VLSI Tech., pp.60-61, 2004
2. W. Landers et al., Proc. of IITC, 6.4, 2004
3. H. Ohtake et al., Proc. of IEDM, pp.853-856, 2003