A 630 MHz, 76 mW direct digital frequency synthesizer using enhanced ROM compression technique

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 350-360

  Strollo, Antonio Giuseppe Maria ^a,b   De Caro, Davide ^a,b   Petra, Nicola ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

DDS; Direct digital frequency synthesis (DDFS); Frequency synthesis; Low power CMOS design; Phase to sinusoid amplitude conversion; ROM compression

Indexed keywords

DIRECT DIGITAL FREQUENCY SYNTHESIS (DDFS); FREQUENCY SYNTHESIS; LOW-POWER CMOS DESIGN; PHASE-TO-SINUSOID AMPLITUDE CONVERSION; ROM COMPRESSION;

ADDERS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; NATURAL FREQUENCIES; ROM;

DIGITAL CIRCUITS;

EID: 33847745869     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889382     Document Type: Article

References (34)

1. B. G. Goldberg, Direct Digital Frequency Synthesis Demystified. Eagle Rock, VA: LLH Technology Publishing, 1999.
2. V. F. Kroupa, Direct Digital Frequency Synthesizer. New York: IEEE Press Book, 1998.
3. J. Vankka and K. Halonen, Direct Digital Synthesizers: Theory, Design and Applications. Norwell, MA: Kluwer Academic, 2001.
4. J. Tierney, C. M. Rader, and B. Gold, "A digital frequency synthesizer," IEEE Trans. Audio Electroacoust., vol. AE-19, no. 1, pp. 48-57, Mar. 1971.
5. H. T. Nicholas and H. Samueli, "An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation," in Proc. 41st Annu. Symp. Frequency Control, May 1987, pp. 495-502.
6. A. Torosyan and A. N. Willson, Jr., "Analysis of the output spectrum for direct digital frequency synthesizers in the presence of phase truncation and finite arithmetic precision," in Proc. 2nd Symp. Image and Signal Processing and Analysis (ISPA01), Pula, Croatia, Jun. 2001, pp. 458-463.
7. F. Curticapean and J. Niittylahti, "Exact analysis of spurious signals in direct digital frequency synthesisers due to phase truncation," Electron. Lett., vol. 39, no. 6, pp. 499-501, Mar. 2003.
8. J. M. P. Langlois and D. Al-Khalili, "Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis," IEE Proc.-Circuits, Devices Syst., vol. 151, no. 6, pp. 519-528, Dec. 2004.
9. A. Madisetti, A. Y. Kwentus, and A. N. Willson, "A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range," IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1034-1043, Aug. 1999.
10. F. Curticapean, K. I. Palomaki, and J. Niittylahti, "Quadrature direct digital frequency synthesizer using an angle rotation algorithm," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS 2003), May 2003, vol. 2, pp. 81-84.
11. Y. Song and B. Kim, "Quadrature direct digital frequency synthesizers using interpolation-based angle rotation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 7, pp. 701-710, Jul. 2004.
12. A. Torosyan, D. Fu, and A. Willson, "A 300 MHz quadrature direct digital synthesizer/mixer in 0.25 μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 875-887, Jun. 2003.
13. Y. Song and B. Kim, "A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1853-1861, Nov. 2004.
14. D. De Caro, N. Petra, and A. G. M. Strollo, "A 380 MHz direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25 μm CMOS,"IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 151-160, Jan. 2007.
15. J. M. P. Langlois and D. AI Khalili, "Novel approach to the design of direct digital frequency synthesizers based on linear interpolation," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, no. 9, pp. 567-578, Sep. 2003.
16. D. De Caro, E. Napoli, and A. G. M. Strollo, "Direct digital frequency synthesizers with polynomial hyperfolding technique," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 7, pp. 337-344, Jul. 2004.
17. A. Bellaouar, M. S. O'Brecht, A. M. Fahim, and M. I. Elmasry, "Low-power direct digital frequency synthesis for wireless communications," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 385-390, Mar. 2000.
18. D. De Caro and A. G. M. Strollo, "High-performance direct digital frequency synthesizers using piecewise-polynomial approximation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2, pp. 324-337, Feb. 2005.
19. _, "High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2220-2227, Nov. 2005.
20. H. T. Nicholas, III and H. Samueli, "A 150-MHz direct digital frequency synthesizer in 1.25-micron CMOS with -90 dBc spurious performance," IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1959-1969, Dec. 1991.
21. B. D. Yang, J. H. Choi, S. H. Han, L. S. Kim, and H. K. Yu, "An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 761-774, May 2004.
22. D. De Caro, N. Petra, and A. G. M. Strollo, "A 630 MHz direct digital frequency synthesizer with 90 dBc SFDR in 0.25 μm CMOS," in IEEE ISSCC 2006 Dig. Tech. Papers, San Francisco, CA, Feb. 2006, pp. 258-259.
23. F. De Dinechin and A. Tisserand, "Multipartite table methods," IEEE Trans. Comput., vol. 54, no. 3, pp. 319-330, Mar. 2005.
24. F. Curticapean and J. Niittylahti, "A hardware efficient direct digital frequency synthesizer," in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Malta, Sep. 2001, pp. 51-54.
25. _, "Low power direct digital frequency synthesizer," in Proc. 43rd IEEE Midwest Symp. Circuits and Systems, Lansing, MI, Aug. 2000, pp. 822-825.
26. J. Fadavi-Ardekani, "M×N Booth encoded multiplier generator using optimized Wallace trees," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 2, pp. 120-125, Jun. 1993.
27. J. M. P. Langlois and D. AI Khalili, "Low power direct digital frequency synthesizer in 0.18 μm CMOS," in Proc. IEEE Custom Integrated Circuits Conf. (CICC 2003), Sep. 2003, pp. 21-24.
28. Y. Song and B. Kim, "A 14-b direct digital frequency synthesizer with sigma-delta noise shaping," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 847-851, May 2004.
29. V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, Apr. 1999.
30. S. Heo, R. Krashinsky, and K. Asanovic, "Activity-sensitive flip-flop and latch selection for reduced energy," in Proc. 19th Conf. Advanced Research in VLSI (ARVLSI 2001), Mar. 2001, pp. 59-74.
31. S. Xue and B. Oelmann, "Comparative study of low-voltage performance of standard-cell flip-flops," in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sep. 2001, vol. 2, pp. 953-957.
32. D. De Caro, E. Napoli, N. Petra, and A. G. M. Strollo, "A high-speed sense-amplifier based flip-flop," in Proc. Eur. Conf. Circuit Theory and Design (ECCTD 2005), Aug.-Sep. 2005, vol. 2, pp. II99-II102.
33. A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, "A novel high-speed sense-amplifier-based flip-flop," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1266-1274, Nov. 2005.
34. J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 62-69, Jan. 1997.