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Volumn 2, Issue , 2001, Pages 953-957

Comparative study of low-voltage performance of standard-cell flip-flops

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG SIMULATIONS; CMOS TECHNOLOGY; COMPARATIVE STUDIES; DESIGN STYLES; HIGH-SPEED PERFORMANCE; LOW POWER; LOW POWER SUPPLY VOLTAGE; LOW-VOLTAGE; MEMORY ELEMENT; POWER SAVINGS; STANDARD CELL; VOLTAGE-SCALING;

EID: 62949137157     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (10)
  • 3
    • 0028565202 scopus 로고
    • A comparative study of single-phase clocked latches using estimation criteria
    • S. Ghannoum, D. Chtchvyrkov, and Y. Savaria, "A comparative study of single-phase clocked latches using estimation criteria, " Proc. of IEEE ISCAS, vol. 6, pp. 347-350, 1994.
    • (1994) Proc. of IEEE ISCAS , vol.6 , pp. 347-350
    • Ghannoum, S.1    Chtchvyrkov, D.2    Savaria, Y.3
  • 4
    • 0342778397 scopus 로고    scopus 로고
    • Latches and flip-flops for low-power systems
    • Edited by A. Chandrakasan and R. Brodersen, IEEE Press
    • C. Svensson and J. Yuan, "Latches and Flip-flops for Low-Power Systems, " Low-Power CMOS Design, Edited by A. Chandrakasan and R. Brodersen, pp. 233-238, IEEE Press 1996.
    • (1996) Low-Power CMOS Design , pp. 233-238
    • Svensson, C.1    Yuan, J.2
  • 5
    • 0033116422 scopus 로고    scopus 로고
    • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
    • V. Stojanovic and V.G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, " IEEE J. of Solid-State Circuits, vol. SC-34, pp. 549-553, 1999.
    • (1999) IEEE J. of Solid-state Circuits , vol.SC-34 , pp. 549-553
    • Stojanovic, V.1    Oklobdzija, V.G.2
  • 6
    • 0029703783 scopus 로고    scopus 로고
    • Design techniques for high-performance, energy-efficient control logic
    • U. Ko, A. Hill, and P. Balsara, "Design Techniques for High-Performance, Energy-Efficient Control Logic, " in ISLPED Dig. Tech. Papers, 1996.
    • (1996) ISLPED Dig. Tech. Papers
    • Ko, U.1    Hill, A.2    Balsara, P.3
  • 7
    • 0030828211 scopus 로고    scopus 로고
    • New single-clock CMOS latches and flip-flops with improved speed and power savings
    • J. Yuan and C. Svensson, "New Single-Clock CMOS Latches and Flip-Flops with Improved Speed and Power Savings, " IEEE J. of Solid-State Circuits, vol. SC-32, 1997.
    • (1997) IEEE J. of Solid-state Circuits , vol.SC-32
    • Yuan, J.1    Svensson, C.2
  • 8
    • 0028733872 scopus 로고
    • A 2.2W, 80MHz superscalar RISC microprocessor
    • G. Gerosa et. al, "A 2.2W, 80MHz Superscalar RISC Microprocessor, " IEEE J. of Solid-State Circuits, vol. 29, pp. 1440-1452, 1994.
    • (1994) IEEE J. of Solid-state Circuits , vol.29 , pp. 1440-1452
    • Gerosa, G.1
  • 10
    • 77949901515 scopus 로고    scopus 로고
    • A static CMOS master-slave flip-flop experiment
    • M. Vesterbacka, "A Static CMOS Master-Slave Flip-Flop Experiment, " Proc. of IEEE ICECS 2000, vol. 2, pp. 870-873, 2000.
    • (2000) Proc. of IEEE ICECS 2000 , vol.2 , pp. 870-873
    • Vesterbacka, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.