A case study in networks-on-chip design for embedded video

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 770-775

  Xu, Jiang ^a   Wolf, Wayne ^a   Henkel, Joerg ^b   Chakradhar, Srimat ^b   Lv, Tiehan ^a  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESSOR-CONTROLLED MODELS; SHARED MEMORIES; SWITCH-BASED ON-CHIP NETWORKS; SYSTEM ON CHIP; DIFFERENT SIZES; MAXIMUM NETWORKS; NETWORKS ON CHIPS; ON-CHIP NETWORKS; PERFORMANCE BOTTLENECKS; REAL COMMUNICATION; SOC (SYSTEM ON CHIP); VIDEO APPLICATIONS;

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SIMULATION; ELECTRIC SWITCHES; MULTIPROCESSING SYSTEMS; OPTIMIZATION; TELECOMMUNICATION NETWORKS; VIDEO SIGNAL PROCESSING; BUSES; CAMERAS; DESIGN; EXHIBITIONS;

EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS;

EID: 3042517230     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. L. Benini, G. De Micheli, "Networks on chip: a new paradigm for systems on chip design", Design, Automation and Test in Europe Conference, 2002.
2. William J. Dally, Brian Towles, "Route packets, not wires: on-chip interconnection networks", Proceedings of the 38th Design Automation Conference, 2001.
3. K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage, "Networks on Silicon: Combining Best-Effort And Guaranteed Services" Design, Automation and Test in Europe Conference, March, 2002.
4. R. Hofmann, B. Drerup, "Next generation CoreConnect processor local bus architecture", Annual IEEE International ASIC/SOC Conference, 25-28 Sept. 2002.
5. D. Flynn, "AMBA: enabling reusable on-chip designs", IEEE Micro, Volume: 17 Issue: 4, July-Aug. 1997
6. D. Wingard, "MicroNetwork-based integration for SOCs", Design Automation Conference, 18-22 June 2001.
7. T. Dumitras, R. Marculescu, "On-chip stochastic communication" Design, Automation and Test in Europe Conference, 2003.
8. M. Galles, "Spider: a high-speed network interconnect", IEEE Micro, Volume: 17 Issue: 1, 1997, Page(s): 34 -39.
9. A. Hemani, A. Jantsch, ect, "Network on chip: An architecture for billion transistor era", Proceeding of the IEEE NorChip Conference, November 2000.
10. Wayne Wolf, Burak Ozer, and Tiehan Lv, "Smart cameras for embedded systems," IEEE Computer, 35(9), September 2002, pp. 48-53.
11. Micron 18Mb SYNCBURST SRAM specification, http://www.micron.com
12. http://www.opnet.com
13. http://www.silicore.net
14. Wayne Wolf, Tiehan Lv, and Burak Ozer, "An Architectural Design Study for a High-Speed Smart Camera", IEEE MICRO MSP-02 Workshop, 2002