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Volumn , Issue , 2002, Pages 198-201

Wave pipelining for application-specific networks-on-chips

Author keywords

Coupling capacitance; Interconnection; Networks on chip (NoC); System on chip (SoC); Wave pipelining

Indexed keywords

APPLICATION-SPECIFIC NETWORK; AREA SAVINGS; COUPLING CAPACITANCE; DATA TRANSPORT; DELAY CONTROL; DESIGN POINTS; ENERGY EFFICIENT; ENERGY SAVING; NETWORKS ON CHIPS; PIPELINED COMMUNICATION; SYSTEM-ON-CHIP; WAVE-PIPELINING;

EID: 4043107598     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581661     Document Type: Conference Paper
Times cited : (12)

References (18)
  • 1
    • 77952980330 scopus 로고    scopus 로고
    • AMBA
    • AMBA http://www.arm.com/arm/AMBA.
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Luca Benini, Giovanni De Micheli, "Networks on chips: A new SoC paradigm", Computer, 35(1): 70-78, 2002.
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 4
    • 0000090413 scopus 로고    scopus 로고
    • An interconnect-centric design flow for nanometer technologies
    • Jason Cong, "An interconnect-centric design flow for nanometer technologies", Proceedings of the IEEE, 89(4): 505-528, 2001.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.4 , pp. 505-528
    • Cong, J.1
  • 5
    • 77953013606 scopus 로고    scopus 로고
    • CoreConnect Bus
    • CoreConnect Bus. http://www-3.ibm.com/chips/techlib/techlib.nsf/ productfamilies/CoreConnect-Bus-Architecture.
  • 8
    • 77953005154 scopus 로고    scopus 로고
    • VLSI system design using asynchronous wave pipelines: A 0.35um CMOS 1.5 GHz elliptic curve public key cryptosystem chip
    • O. Hauck, A. Katoch, S.A. Huss, "VLSI system design using asynchronous wave pipelines: a 0.35um CMOS 1.5 GHz elliptic curve public key cryptosystem chip", ASYNC 2000, 188-197, 2000.
    • (2000) ASYNC 2000 , pp. 188-197
    • Hauck, O.1    Katoch, A.2    Huss, S.A.3
  • 14
    • 14544283845 scopus 로고    scopus 로고
    • A self-timed wave pipelined adder using data align method
    • Byoung-Hoon Lim, Jin-Ku Kang, "A self-timed wave pipelined adder using data align method", AP-ASIC 2000, 77-80, 2000.
    • (2000) AP-ASIC 2000 , pp. 77-80
    • Lim, B.-H.1    Kang, J.-K.2
  • 15
    • 77953017736 scopus 로고    scopus 로고
    • RAW architecture. http://www.cag.lcs.mit.edu/raw/documents.
    • RAW Architecture
  • 18
    • 4143052654 scopus 로고
    • Designing high performance digital circuits using wave pipelining: Algorithms and practical experiences
    • Jan.
    • D. Wong, G. De Micheli, M. Flynn, "Designing high performance digital circuits using wave pipelining: Algorithms and practical experiences", IEEE Trans. Computer-Aided Design, 12(1): 25-46, Jan. 1993.
    • (1993) IEEE Trans. Computer-Aided Design , vol.12 , Issue.1 , pp. 25-46
    • Wong, D.1    De Micheli, G.2    Flynn, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.