Overview of oversampling clock and data recovery circuits

Canadian Conference on Electrical and Computer Engineering

Volumn 2005, Issue , 2005, Pages 1876-1881

  Ahmed, S I ^a   Kwasniewski, Tad A ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

CDR; DR; Jitter tolerance; Oversampling; PLL

Indexed keywords

EYE TRACKING ARCHITECTURE; JITTER TOLERANCE; MULTIPLE ROTATING PHASES; NON RETURN TO ZERO (NRZ);

COMPUTER ARCHITECTURE; JITTER; PHASE LOCKED LOOPS; TRACKING (POSITION);

DIGITAL CIRCUITS;

EID: 33751314584     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2005.1557348     Document Type: Conference Paper

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