Fractional rate phase detectors for clock and data recovery

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 313-316

  Seedher, A ^a,b   Sobelman, G E ^a  

^a University of Minnesota   (United States)

^b TEXAS INSTRUMENTS   (India)

Author keywords

Circuits; Clocks; CMOS process; CMOS technology; Latches; Optical fiber communication; Phase detection; Phase frequency detector; Phase locked loops; Voltage controlled oscillators

Indexed keywords

CIRCUIT OSCILLATIONS; CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS); CLOCKS; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; FLIP FLOP CIRCUITS; NETWORKS (CIRCUITS); OPTICAL COMMUNICATION; OPTICAL FIBER COMMUNICATION; OPTICAL FIBERS; OSCILLATORS (ELECTRONIC); OSCILLISTORS; PHASE LOCKED LOOPS; SIGNAL DETECTION; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY; CMOS PROCESS TECHNOLOGY; CMOS PROCESSS; CMOS TECHNOLOGY; MAXIMUM OPERATING FREQUENCY; PHASE DETECTION; PHASE DETECTORS; PHASE FREQUENCY DETECTORS;

TIMING CIRCUITS;

EID: 33751341496     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241533     Document Type: Conference Paper

References (11)

1. J. Savoj, B. Razavi, "High-Speed CMOS Circuits for Optical Receivers," Kluwer Academic Publishers, 2001.
2. J. Savoj, B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector," IEEE Journal of Solid-State Circuits, pp. 761-768, May 2001.
3. J. Savoj and B. Razavi, "Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems," Design Automation Conference, pp. 121-126, 2001.
4. J. Savoj and B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit," Symposium on VLSI Circuits, pp. 136-139, 2000.
5. J. Savoj and B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Binary Phase/Frequency Detector," IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, pp. 13-21, 2003.
6. B. Razavi, "Challenges in the Design of High-Speed Clock and Data Recovery Circuits," IEEE Communications Magazine, Vol. 40, No. 8, pp. 94-101, 2002.
7. M. Wurzer, et al., "40-Gb/s Integrated Clock and Data Recovery Circuit in a Silicon Bipolar Technology," Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, pp. 136-139, Sept. 1998.
8. M. Rau, et al., "Clock/Data Recovery PLL using Half-Frequency Clock," IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1156-1159, July 1997.
9. P. Larsson, "An Offset-Cancelled CMOS Clock-Recovery/Demux with a Half-Rate Linear Phase Detector for 2.5 Gb/s Optical Communication," IEEE International Solid-State Circuits Conference, pp. 74-75 and 434, 2001.
10. M. Ramezani et al, "Analysis of a Half-Rate Bang-Bang Phase-Locked-Loop," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 7, pp. 505-509, 2002.
11. J. Rogers and J. Long, "A 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18-μ CMOS," IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1781-1789, 2002.