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Volumn 50, Issue 11, 2003, Pages 775-783

Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery

Author keywords

Clock and data recovery (CDR); Effective phase detector gain; Tracked oversampling

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; DATA REDUCTION; ELECTRIC CLOCKS; ERROR ANALYSIS; PROBABILITY DISTRIBUTIONS; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION LINKS;

EID: 0345724749     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819070     Document Type: Article
Times cited : (41)

References (15)
  • 1
    • 0022187594 scopus 로고
    • A self-correcting clock recovery circuits
    • Dec.
    • C. Hogge, "A self-correcting clock recovery circuits," J. Lightwave Technol., vol. LT-3, pp. 1312-1314, Dec. 1985.
    • (1985) J. Lightwave Technol. , vol.LT-3 , pp. 1312-1314
    • Hogge, C.1
  • 2
    • 0035054818 scopus 로고    scopus 로고
    • A 10-Gb/s CMOS clock and data recovery circuit with frequency detection
    • Feb.
    • J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with frequency detection," in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 78-79.
    • (2001) ISSCC Dig. Tech. Papers , pp. 78-79
    • Savoj, J.1    Razavi, B.2
  • 4
    • 0016565959 scopus 로고
    • Clock recovery from random binary signals
    • Oct.
    • J. D. H. Alexander, "Clock recovery from random binary signals," Electron. Lett., vol. 11, pp. 541-542, Oct. 1975.
    • (1975) Electron. Lett. , vol.11 , pp. 541-542
    • Alexander, J.D.H.1
  • 5
    • 0036105878 scopus 로고    scopus 로고
    • A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS
    • Feb.
    • J. E. Rogers and J. R. Long, "A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 254-255.
    • (2002) ISSCC Dig. Tech. Papers , pp. 254-255
    • Rogers, J.E.1    Long, J.R.2
  • 6
    • 0031073621 scopus 로고    scopus 로고
    • A 1.0625 Gbps transceiver with 2 ×-oversampling and transmit signal pre-emphasis
    • Feb.
    • A. Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625 Gbps transceiver with 2 ×-oversampling and transmit signal pre-emphasis," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 238-239.
    • (1997) ISSCC Dig. Tech. Papers , pp. 238-239
    • Fiedler, A.1    Mactaggart, R.2    Welch, J.3    Krishnan, S.4
  • 7
    • 0000137737 scopus 로고    scopus 로고
    • A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS tranceiver
    • Feb.
    • R. Gu, J. M. tran, H.-C. Lin, A.-L. Yee, and M. Izzard, "A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS tranceiver," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 352-353.
    • (1999) ISSCC Dig. Tech. Papers , pp. 352-353
    • Gu, R.1    Tran, J.M.2    Lin, H.-C.3    Yee, A.-L.4    Izzard, M.5
  • 9
    • 0030081924 scopus 로고    scopus 로고
    • A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array
    • Feb.
    • I. Lee, C. Yoo, W. Kim, S. Chai, and W. Song, "A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 198-199.
    • (1996) ISSCC Dig. Tech. Papers , pp. 198-199
    • Lee, I.1    Yoo, C.2    Kim, W.3    Chai, S.4    Song, W.5
  • 11
    • 0035054799 scopus 로고    scopus 로고
    • A 0.6 - 2.5 Gbaud CMOS tracked 3 × oversampling transceiver with dead zone phase detection for robust clock/data recovery
    • Feb.
    • Y. Moon, D.-K. Jeong, and G. Ahn, "A 0.6 - 2.5 Gbaud CMOS tracked 3 × oversampling transceiver with dead zone phase detection for robust clock/data recovery," in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 212-213.
    • (2001) ISSCC Dig. Tech. Papers , pp. 212-213
    • Moon, Y.1    Jeong, D.-K.2    Ahn, G.3
  • 12
    • 0038306651 scopus 로고    scopus 로고
    • A 2.5-10 Gb/s CMOS transceiver with alternating edge sampling phase detector for loop characteristic stabilization
    • Feb.
    • B.-J. Lee, M.-S. Hwang, S. Lee, and D.-K. Jeong, "A 2.5-10 Gb/s CMOS transceiver with alternating edge sampling phase detector for loop characteristic stabilization," in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 76-77.
    • (2003) ISSCC Dig. Tech. Papers , pp. 76-77
    • Lee, B.-J.1    Hwang, M.-S.2    Lee, S.3    Jeong, D.-K.4
  • 14
    • 0345374790 scopus 로고    scopus 로고
    • SONET OC-192 Transport System Generic Criteria
    • Telcordia, Piscataway, NJ, Mar.
    • "SONET OC-192 Transport System Generic Criteria," Telcordia, Piscataway, NJ, Tech. Rep. GR-1377-CORE, Mar. 1998.
    • (1998) Tech. Rep. , vol.GR-1377-CORE
  • 15
    • 0036053142 scopus 로고    scopus 로고
    • Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits
    • June
    • M. H. Perrott, "Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits," in Proc. Design Automation Conf., June 2002, pp. 498-503.
    • (2002) Proc. Design Automation Conf. , pp. 498-503
    • Perrott, M.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.