A pipelined serial data receiver with oversampling techniques for high-speed data communications

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 167-170

  Lin, Yih Horng ^a   Tu, Steve Hung Lung ^a  

^a FU JEN CATHOLIC UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRON DEVICES; JITTER; PHASE LOCKED LOOPS;

DATA RECOVERY; FEED FORWARD; HIGH-BANDWIDTH APPLICATION; HIGH-SPEED DATA COMMUNICATION; NON-RETURN TO ZEROS; OVER SAMPLING; OVERSAMPLING TECHNIQUE; PIPELINED ARCHITECTURE;

SOLID STATE DEVICES;

EID: 84946413707     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283507     Document Type: Conference Paper

References (5)

1. H. Braunisch and Raj Nair, "On the Techniques of Clock Extraction and Oversampling," Hot Interconnects 9, pp.139-143, Aug. 2001.
2. B. C. O'Neill, S. Clark and K. L. Wong, "Serial Communication Circuit with Optimized Skew Characterics," IEEE Communications Letters, Vol.5, No.6, pp.260-262, June 2001.
3. Kyeongho Lee, Sungjoon Kim, Gijung Ahn and Deog-Kyoon Jeong, "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE Journal of Solid-State Circuits, Vol.30, No.4, pp.353-364, April 1995.
4. Yongsam Moon, Deog-Kyoon Jeong and Gijung Ahn, "A 0.6-2.5 Gbaud CMOS Tracked 3X Oversampling Transceiver with Dead-Zone Phase Detector for Robust Clock/Data Recovery," IEEE Journal of Solid-State Circuits, Vol.36, No.12, pp.1974-1983, Dec. 2001.
5. Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz "A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling," IEEE Journal of Solid-State Circuits, Vol.33, No.5, page 713-722, May 1998