A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 3, 2001, Pages 432-439

  Anand, Seema ^a   Razavi, Behzad ^a  

^a University of California   (United States)

Author keywords

Clock and data recovery; Optical communication; Oscillators; Phase detectors; PLLs

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; JITTER; OPTICAL COMMUNICATION; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

CLOCK RECOVERY CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035273843     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.910482     Document Type: Article

References (9)

1. Properties of frequency difference detectors
2. A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s
3. Robust two-stage current-controlled oscillator in sub-micrometer CMOS
4. A 3.3-V high-speed CMOS PLL with a two-stage self-feedback ring oscillator
5. A monolithic 622 Mb/s clock extraction data retiming circuit
6. A self correcting clock recovery circuit
7. A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology
8. SiGe clock and data recovery IC with linear-type PLL fir 10-Gb/s SONET application
9. A versatile clock recovery architecture and monolithic implementation