Clock and data recovery circuits with fast acquisition and low jitter

IEEE Workshop on Microelectronics and Electron Devices, WMED: IEEE Electron Devices Northwest Regional Meeting

Volumn , Issue , 2004, Pages 48-51

  Zhang, Ruiyuan ^a   La Rue, George S ^a  

^a WASHINGTON STATE UNIVERSITY   (United States)

Author keywords

Clock recovery; Delay locked loops (DLL); Fast locking time; Phase locked loops (PLL)

Indexed keywords

CLOCK AND DATA RECOVERY CIRCUITS (CDR); CLOCK RECOVERY; DELAY-LOCKED LOOPS (DLL); FAST LOCKING TIME;

CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; DELAY CIRCUITS; ELECTRIC CLOCKS; FEEDBACK; INTERPOLATION; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

JITTER;

EID: 3042616189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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