Self-aligned metal capping layers for copper interconnects using electroless plating

Microelectronic Engineering

Volumn 83, Issue 11-12, 2006, Pages 2059-2067

  Gambino, J ^a   Wynne, J ^a   Gill, J ^a   Mongeon, S ^a   Meatyard, D ^a   Lee, B ^b   Bamnolker, H ^b   Hall, L ^b   Li, N ^b   Hernandez, M ^b   Little, P ^b   Hamed, M ^b   Ivanov, I ^b   Gan, C L ^c  

^a IBM MICROELECTRONICS   (United States)

^b Blue29 LLC   (United States)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER; ELECTROLESS PLATING; IMAGE SENSORS; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS;

ELECTRON FLOW; LOGIC CHIPS; METAL CAPPING LAYERS; STRIP CHEMISTRY;

SELF ASSEMBLY;

EID: 33751226633     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2006.09.008     Document Type: Article

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