-
2
-
-
84962184017
-
An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors
-
A. Aggarwal and M. Franklin. An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. In Proceedings of ISPASS, 2001.
-
(2001)
Proceedings of ISPASS
-
-
Aggarwal, A.1
Franklin, M.2
-
4
-
-
0034839435
-
Power and energy reduction via pipeline balancing
-
July
-
R. I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In Proceedings of ISCA-28, pages 218-229, July 2001.
-
(2001)
Proceedings of ISCA-28
, pp. 218-229
-
-
Bahar, R.I.1
Manne, S.2
-
5
-
-
8344258257
-
Cluster prefetch: Tolerating on-chip wire delays in clustered microarchitectures
-
June
-
R. Balasubramonian. Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures. In Proceedings of ICS-18, June 2004.
-
(2004)
Proceedings of ICS-18
-
-
Balasubramonian, R.1
-
6
-
-
0038346226
-
Dynamically managing the communication-parallelism trade-off in future clustered processors
-
June
-
R. Balasubramonian, S. Dwarkadas, and D. Albonesi. Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. In Proceedings of ISCA-30, pages 275-286, June 2003.
-
(2003)
Proceedings of ISCA-30
, pp. 275-286
-
-
Balasubramonian, R.1
Dwarkadas, S.2
Albonesi, D.3
-
7
-
-
0034462014
-
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
-
December
-
A. Baniasadi and A. Moshovos. Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors. In Proceedings of MICRO-33, pages 337-347, December 2000.
-
(2000)
Proceedings of MICRO-33
, pp. 337-347
-
-
Baniasadi, A.1
Moshovos, A.2
-
9
-
-
0034316092
-
Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
-
November/December
-
D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta, and P. Cook. Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro, November/December 2000.
-
(2000)
IEEE Micro
-
-
Brooks, D.1
Bose, P.2
Schuster, S.3
Jacobson, H.4
Kudva, P.5
Buyuktosunoglu, A.6
Wellman, J.7
Zyuban, V.8
Gupta, M.9
Cook, P.10
-
10
-
-
0033719421
-
Wattch: A frame-work for architectural-level power analysis and optimizations
-
June
-
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Frame-work for Architectural-Level Power Analysis and Optimizations. In Proceedings of ISCA-27, pages 83-94, June 2000.
-
(2000)
Proceedings of ISCA-27
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
13
-
-
0038026366
-
Dynamic code partitioning for clustered architectures
-
R. Canal, J. M. Parcerisa, and A. Gonzalez. Dynamic Code Partitioning for Clustered Architectures. International Journal of Parallel Programming, 29(1):59-79, 2001.
-
(2001)
International Journal of Parallel Programming
, vol.29
, Issue.1
, pp. 59-79
-
-
Canal, R.1
Parcerisa, J.M.2
Gonzalez, A.3
-
15
-
-
33750801788
-
Dynamically matching ILP characteristics via a heterogeneous clustered microarchitecture
-
October
-
L. Chen, D. Albonesi, and S. Drophso. Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture. In IBM Watson Conference on the Interaction between Architecture, Circuits and Compilers, pages 136-143, October 2004.
-
(2004)
IBM Watson Conference on the Interaction between Architecture, Circuits and Compilers
, pp. 136-143
-
-
Chen, L.1
Albonesi, D.2
Drophso, S.3
-
18
-
-
12444282715
-
Clustered multithreaded architectures - Pursuing both IPC and cycle time
-
April
-
J. Collins and D. Tullsen. Clustered Multithreaded Architectures - Pursuing Both IPC and Cycle Time. In Proceedings of the 18th IPDPS, April 2004.
-
(2004)
Proceedings of the 18th IPDPS
-
-
Collins, J.1
Tullsen, D.2
-
19
-
-
0036292415
-
Managing multi-configurable hardware via dynamic working set analysis
-
May
-
A. Dhodapkar and J. E. Smith. Managing Multi-Configurable Hardware via Dynamic Working Set Analysis. In Proceedings of ISCA-29, pages 233-244, May 2002.
-
(2002)
Proceedings of ISCA-29
, pp. 233-244
-
-
Dhodapkar, A.1
Smith, J.E.2
-
20
-
-
0031374601
-
The multicluster architecture: Reducing cycle time through partitioning
-
December
-
K. Farkas, P. Chow, N. Jouppi, and Z. Vranesic. The Multicluster Architecture: Reducing Cycle Time through Partitioning. In Proceedings of MICRO-30, pages 149-159, December 1997.
-
(1997)
Proceedings of MICRO-30
, pp. 149-159
-
-
Farkas, K.1
Chow, P.2
Jouppi, N.3
Vranesic, Z.4
-
21
-
-
2942665573
-
-
Technical report, Transmeta Corporation, January
-
M. Fleischmann. Longrun Power Management. Technical report, Transmeta Corporation, January 2001.
-
(2001)
Longrun Power Management
-
-
Fleischmann, M.1
-
25
-
-
84944397775
-
Flexible compiler-managed LO buffers for clustered VLIW processors
-
December
-
E. Gibert, J. Sanchez, and A. Gonzalez. Flexible Compiler-Managed LO Buffers for Clustered VLIW Processors. In Proceedings of MICRO-36, December 2003.
-
(2003)
Proceedings of MICRO-36
-
-
Gibert, E.1
Sanchez, J.2
Gonzalez, A.3
-
26
-
-
0038346237
-
Positional adaptation of processors: Applications to energy reduction
-
June
-
M. Huang, J. Renau, and J. Torrellas. Positional Adaptation of Processors: Applications to Energy Reduction. In Proceedings of ISCA-30, pages 157-168, June 2003.
-
(2003)
Proceedings of ISCA-30
, pp. 157-168
-
-
Huang, M.1
Renau, J.2
Torrellas, J.3
-
27
-
-
28444484731
-
More on finding a single number to indicate over-all performance of a benchmark suite
-
March
-
L. John. More on Finding a Single Number to Indicate Over-all Performance of a Benchmark Suite. ACM Computer Architecture News, 32(1), March 2004.
-
(2004)
ACM Computer Architecture News
, vol.32
, Issue.1
-
-
John, L.1
-
28
-
-
0036396915
-
The imagine stream processor
-
September
-
U. Kapasi, W. Dally, S. Rixner, J. Owens, and B. Khailany. The Imagine Stream Processor. In Proceedings of ICCD, September 2002.
-
(2002)
Proceedings of ICCD
-
-
Kapasi, U.1
Dally, W.2
Rixner, S.3
Owens, J.4
Khailany, B.5
-
29
-
-
0036292594
-
An instruction set and microarchitecture for instruction level distributed processing
-
May
-
H.-S. Kim and J. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In Proceedings of ISCA-29, May 2002.
-
(2002)
Proceedings of ISCA-29
-
-
Kim, H.-S.1
Smith, J.2
-
30
-
-
84944403811
-
Single ISA heterogeneous multi-core architectures: The potential for processor power reduction
-
December
-
R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen. Single ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In Proceedings of the 36th International Symposium on Micro-Architecture, December 2003.
-
(2003)
Proceedings of the 36th International Symposium on Micro-architecture
-
-
Kumar, R.1
Farkas, K.2
Jouppi, N.3
Ranganathan, P.4
Tullsen, D.5
-
32
-
-
34247352753
-
Performance, power efficiency, and scalability of asymmetric cluster chip multiprocessors
-
January
-
T. Morad, U. Weiser, A. Kolodny, M. Valero, and E. Ayguade. Performance, Power Efficiency, and Scalability of Asymmetric Cluster Chip Multiprocessors. Technical Report CCIT Technical Report #514, January 2005.
-
(2005)
Technical Report CCIT Technical Report #514
-
-
Morad, T.1
Weiser, U.2
Kolodny, A.3
Valero, M.4
Ayguade, E.5
-
33
-
-
0035693945
-
A design space evaluation of grid processor architectures
-
December
-
R. Nagarajan, K. Sankaralingam, D. Burger, and S. Keckler. A Design Space Evaluation of Grid Processor Architectures. In Proceedings of MICRO-34, pages 40-51, December 2001.
-
(2001)
Proceedings of MICRO-34
, pp. 40-51
-
-
Nagarajan, R.1
Sankaralingam, K.2
Burger, D.3
Keckler, S.4
-
35
-
-
0002432406
-
The case for a single-chip multiprocessor
-
October
-
K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson, and K.-Y. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of ASPLOS-VII, October 1996.
-
(1996)
Proceedings of ASPLOS-VII
-
-
Olukotun, K.1
Nayfeh, B.2
Hammond, L.3
Wilson, K.4
Chang, K.-Y.5
-
37
-
-
0035691607
-
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
-
December
-
D. Ponomarev, G. Kucuk, and K. Ghose. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources. In Proceedings of MICRO-34, pages 90-101, December 2001.
-
(2001)
Proceedings of MICRO-34
, pp. 90-101
-
-
Ponomarev, D.1
Kucuk, G.2
Ghose, K.3
-
38
-
-
1142280992
-
Partitioned first-level cache design for clustered microarchitectures
-
June
-
P. Racunas and Y. Patt. Partitioned First-Level Cache Design for Clustered Microarchitectures. In Proceedings of ICS-17, June 2003.
-
(2003)
Proceedings of ICS-17
-
-
Racunas, P.1
Patt, Y.2
-
39
-
-
0034459218
-
Modulo scheduling for a fully-distributed clustered VLIW architecture
-
December
-
J. Sanchez and A. Gonzalez. Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture. In Proceedings of MICRO-33, pages 124-133, December 2000.
-
(2000)
Proceedings of MICRO-33
, pp. 124-133
-
-
Sanchez, J.1
Gonzalez, A.2
-
40
-
-
0345272496
-
Energy efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
-
February
-
G. Semeraro, G. Magklis, R. Balasubramonian, D. Albonesi, S. Dwarkadas, and M. Scott. Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In Proceedings of HPCA-8, pages 29-40, February 2002.
-
(2002)
Proceedings of HPCA-8
, pp. 29-40
-
-
Semeraro, G.1
Magklis, G.2
Balasubramonian, R.3
Albonesi, D.4
Dwarkadas, S.5
Scott, M.6
-
43
-
-
0038684860
-
Temperature-aware microarchitecture
-
June
-
K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-Aware Microarchitecture. In Proceedings of ISCA-30, June 2003.
-
(2003)
Proceedings of ISCA-30
-
-
Skadron, K.1
Stan, M.2
Huang, W.3
Velusamy, S.4
Sankaranarayanan, K.5
Tarjan, D.6
-
44
-
-
0034817930
-
Dynamic prediction of critical path instructions
-
January
-
E. Tune, D. Liang, D. Tullsen, and B. Calder. Dynamic Prediction of Critical Path Instructions. In Proceedings of HPCA-7, pages 185-196, January 2001.
-
(2001)
Proceedings of HPCA-7
, pp. 185-196
-
-
Tune, E.1
Liang, D.2
Tullsen, D.3
Calder, B.4
-
45
-
-
0034825598
-
An integrated circuit/architecture approach to reducing leakage in deep submicron high-performance I-caches
-
January
-
S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep Submicron High-Performance I-Caches. In Proceedings of HPCA-7, pages 147-158, January 2001.
-
(2001)
Proceedings of HPCA-7
, pp. 147-158
-
-
Yang, S.1
Powell, M.2
Falsafi, B.3
Roy, K.4
Vijaykumar, T.5
-
46
-
-
34249306904
-
-
Technical Report CS-2003-05, Univ. of Virginia, March
-
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, Univ. of Virginia, March 2003.
-
(2003)
HotLeakage: A Temperature-aware Model of Subthreshold and Gate Leakage for Architects
-
-
Zhang, Y.1
Parikh, D.2
Sankaranarayanan, K.3
Skadron, K.4
Stan, M.5
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