Dynamic cluster assignment mechanisms

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 133-142

  Canal, Ramon ^a   Parcerisa, Joan Manuel ^a   Gonzalez, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); INTEGER PROGRAMMING; LOGIC DESIGN; MICROPROCESSOR CHIPS; MICROPROGRAMMING; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS);

CLUSTERED MICROARCHITECTURE; DYNAMICALLY SCHEDULED PROCESSORS; FLOATING POINT INSTRUCTIONS; INTER CLUSTER COMMUNICATION PENALTY; STEERING LOGIC; SUPERSCALAR PROCESSORS; WIRE DELAYS; WORKLOAD BALANCE;

COMPUTER ARCHITECTURE;

EID: 0033325736     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)