A review of yield modelling techniques for semiconductor manufacturing

International Journal of Production Research

Volumn 44, Issue 23, 2006, Pages 5019-5036

  Kumar, N ^a   Kennedy, K ^b   Gildersleeve, K ^b   Abelson, R ^b   Mastrangelo, C M ^a   Montgomery, D C ^b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b Arizona State University   (United States)

Author keywords

Semiconductor manufacturing; Yield modelling

Indexed keywords

MATHEMATICAL MODELS; PROFESSIONAL ASPECTS; QUALITY CONTROL; SEMICONDUCTOR MATERIALS; SYSTEMS ANALYSIS; WSI CIRCUITS;

SEMICONDUCTOR MANUFACTURING; YIELD LOSSES; YIELD MODELING TECHNIQUES;

PRODUCTION ENGINEERING;

EID: 33750341424     PISSN: 00207543     EISSN: 1366588X     Source Type: Journal    
DOI: 10.1080/00207540600596874     Document Type: Review

References (64)

1. Balasubramaniam, S., Sarwar, A.K. and Walker, D.M.H., Yield learning in integrated circuit package assembly. IEEE Trans. Compon. Packag. Manuf. Technol. C, 1997, 20(2), 133-141.
2. Boning, D., Chung, J., Ouma, D. and Divecha, R., Spatial variation in semiconductor processes: modeling for control, in Proceedings of the Second International Symposium on Process Control, Diagnostics, and Modelling in Semiconductor Manufacturing, Montreal, May 1997, pp. 72-83.
3. Boning, D. and Chung, J., Statistical metrology-measurement and modeling of variation for advanced process development and design rule generation. AIP Conf. Proc, 1998, pp. 395-404.
4. Butler, S.W., Process control in semiconductor manufacturing. J. Vac. Sci. Technol. B. 1995, 13(4), 1917-1923.
5. Chatterjee, A., Nurani, R.K., Seshadri, S. and Shanthikumar, J.G., Role of yield management in fabless-foundry partnerships. IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, 1997, 6/8, 31-34.
6. Chaudhry, N., Moyne, J. and Rundensteiner, E.A., Active controller: utilising active databases for implementing multistep control of semiconductor manufacturing. IEEE Trans. Compon. Packag. Manuf. Technol. C. 1998, 21(3). 217-224.
7. Chen, H., Harrison, J.M. Mandelbaum, A. and Wein Lawrence, M., Empirical evaluation of a queueing network model for semiconductor wafer fabrication. Oper. Res., 1988, 36(2), 202-215.
8. Chung, K. and Sang, C.P., A machine learning approach to yield management in semiconductor manufacturing. Int. J. Prod. Res., 2000, 38(17). 4261-4271.
9. Cunningham, J.A., The use and evaluation of yield models in integrated circuit manufacturing. IEEE Trans. Semicon. Manuf., May 1990, 3(2), 60-71.
10. Cunningham, S.P., Spanos, C.J. and Voros, K., Semiconductor yield improvement: results and best practices. IEEE Trans. Semicon. Manuf., 1995, 8(2), 103-109.
11. Del Castillo, E., Statistical process adjustment for quality control, 2002 (Wiley-Interscience: New York, NY).
12. Doniavi, A., Mileham, A.R. and Newnes, L.B., A systems approach to modelling in the manufacturing environment, in Proceedings of the 12th National Conference on Manufacturing Research, Bath, September 1996, pp. 111-115.
13. Doniavi, A., Mileham, A.R. and Newnes, L.B., A systems approach to photolithography process optimisation in an electronics manufacturing environment. Int. J. Prod. Res., 2000, 38(11), 2515-2528.
14. Durbeck, D., Chern, J.H. and Boning, D., A system for semiconductor process specification. IEEE Trans. Semicon. Manuf., November 1993, 6, 297-305.
15. Edgar, T.F., Campbell, W.J. and Bode, C., Model-based control in microelectronics manufacturing, in Proceedings of the 38th IEEE Conference on Decision and Control, 1999, pp. 4185-4191.
16. Ferris-Prabhu, A.V. Smith, L.D., Bonges, H.A. and Paulsen, J.K., Radial yield variations in semiconductor wafers. IEEE Circuits Devices Mag., March 1987, 3, 42-47.
17. Ferris-Prabhu, A.V., On the assumptions contained in semiconductor yield models. IEEE Trans. CAD Integ. Circuits Syst., 1992, 11(8), 966-975.
18. Flack, F.V., Introducing dependency into IC yield models. Solid-State Electron., 1985, 28(6), 555-559.
19. Gandemer, S., Tremintin, B.C. and Charlot, J.J., Critical area and critical levels calculation in I.C. yield modeling. IEEE Trans. Electron. Dev., 1988, 35(2), 158-166.
20. Gardner, R.M., Bieker, J. and Elwell, S., Solving tough semiconductor manufacturing problems using data mining, in IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. 2000, pp. 46-55.
21. Guo, H.F., Spanos, C.J. and Miller, A.J., Real time statistical process control for plasma etching, in IEEE/SEMI International Semiconductor Manufacturing Science Symposium, 1991, pp. 113-118.
22. Gupta, A., Porter, W.A. and Lathrop, J.W., Defect analysis and yield degradation of integrated circuits. IEEE J. Solid-State Circuits, 1974, 9(3), 96-102.
23. Harvey E.H., Mastrangelo, C.M. and White K.P., Evaluation of spatial randomness model for yield analysis. IEEE Trans. Semicon. Manuf., 2005 (submitted).
24. Hess, C. and Weiland, L.H., Extraction of wafer-level defect density distributions to improve yield prediction. IEEE Trans. Semicon. Manuf., 1999, 12(2), 175-183.
25. Horton, D., Modeling the yield of mixed-technology die. Solid State Tech., September 1998, 41(9), 109-119.
26. Khan, K., Solakhain, V., Ricci, A., Gu, T. and Moyne, J., Run-to-run control of ITO deposition process. Proceedings of SID, May 1998, 29, 536-539.
27. Koren, I. and Koren, Z., Defect tolerance in VLSI circuits: techniques and yield analysis. Proc. IEEE, 1998, 86(9), 1819-1838.
28. Kristoff, P. and Nunn, D., The process specification system for MMST. IEEE Trans. Semicon. Manuf., August 1995, 8, 262-271.
29. Leachman, R.C., The competitive semiconductor manufacturing survey, in IEEE International Symposium on Semiconductor Manufacturing Conference, 1993, pp. 0359-0381.
30. Lee, F., Wang, P. and Goodner, R., Factory start-up and production ramp: yield improvement through signature analysis and visual/electrical correlation, in IEEE/SEMI Proceedings Advanced Semiconductor Manufacturing Conference and Workshop, November 1995, pp. 267-270.
31. Lee, S.F., Boskin, E.D., Hao, C.L., Wen, E.H. and Spanos, C.J., RTSPC: A software utility for real-time SPC and tool data analysis. IEEE Trans. Semicon. Manuf., February 1995, 8(1), 17-25.
32. Lee, S.F. and Spanos, C.J., Prediction of wafer state after plasma processing using real-time tool data. IEEE Trans. Semicon. Manuf., 1995, 8(3), 252-261.
33. Longtin, M.D., Wein, L.M. and Welsch, R.E., Sequential screening in semiconductor manufacturing. I: exploiting spatial dependence. Oper. Res., 1996, 44(1), 173-195.
34. Mallory, C.L., Perloff, D.S., Hasan, T.F. and Stanley, R.M., Spatial yield analysis in integrated circuit manufacturing. Solid State Technol., November 1983, 26, 121-127.
35. Maynard, D., Bombardier, S., Cavanaugh, A. and Zwonik, R., Modeling and optimisation of wafer radial yield, in IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, 1999, pp. 71-75.
36. Moyne, J., Telfeyan, R. Hurwitz, A. and Taylor, J., A process-independent run-to-run controller and its application to chemical-mechanical planarisation, in IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, 1995, pp. 194-200.
37. Moyne, J., Del Castillo, E. and Hurwitz, A.M., Run-to-Run Control in Semiconductor Manufacturing, 2000 (CRC Press: Florida).
38. Murphy, B., Cost-size optima of monolithic integrated circuits. Proc. IEEE, 1964, 52(12), 1537-1545.
39. Newnes, L.B., Mileham, T.R. and Doniavi, A., A systems approach to semiconductor optimisation. IEEE Trans. Electron. Packag. Manuf., 2001, 24(3), 171-177.
40. Nurani, R.K., Akella, R. and Strojwas, A.J., In-line defect sampling methodology in yield management: an integrated framework. IEEE Trans. Semicon. Manuf., 1996, 9(4), 506-517.
41. Nurani, R.K., Strojwas, A.J., Maly, W.P., Ouyang, C., Shindo, W., Akella, R., McIntyre, M.G. and Derrett, J., In-line yield prediction methodologies using patterned wafer inspection information. IEEE Trans. Semicon. Manuf., February 1998, 11(1), 40-47.
42. Okabe, T., Nagata, M. and Shimada, S., Analysis of yield of integrated circuits and a new expression of the yield. Elect. Eng. in Japan, 1972, 92, 135-141.
43. Peikert, A., Thoma, J. and Brown, S., Rapid modeling technique for measurable improvements in factory performance. IEEE Winter Simul. Conf. Proc., 1998, 2, 1011-1015.
44. Price, J.E., A new look at yield of integrated circuits. Proc. IEEE, August 1970, 58, 1290-1291.
45. Quirk, M. and Serda, J., Semiconductor Manufacturing Technology, 2001 (Prentice Hall: New Jersey).
46. Radojcic, R. and Rencher, M., Old rules no longer apply (what has yield got to do with IC design?). EE Times, 2000 (submitted).
47. Sack, E.A., Global yield engineering for IC production. Solid State Tech., 1998, 41(12), 81-85.
48. Seeds, R.B., Yield and cost analysis of bipolar LSI. IEEE International Electron Devices Meeting 1967, p. 12.
49. Skinner, K.R., Montgomery, D.C., Runger, G.C., Fowler, J.W., McCarville, D.R., Rhoads, T.R. and Stanley, J.D., Multivariate statistical methods for modeling and analysis of wafer probe lest data. IEEE Trans. Semicon. Manuf., 2002, 15(4), 523-530.
50. Stapper, C.H., LSI yield modeling and process monitoring. IBM J. Res. Dev., 1976, 20(3), 228-234.
51. Stapper, C.H., The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions. IBM J. Res. Dev., 1985, 29(1), 87-97.
52. Stapper, C.H., Fact and fiction in yield modeling. Microelectron. J., 1989, 20(1/2), 129-151.
53. Stapper, C.H., On Murphy's yield integral. IEEE Trans. Semicon. Manuf., 1991, 3(2), 294-298.
54. Stapper, C.H. and Rosner, R.J., Integrated circuit yield management and yield analysis; development and implementation. IEEE Trans. Semicon. Manuf., 1995, 8(2), 95-102.
55. Spanos, C.J., Statistical process control in semiconductor manufacturing. Proc. IEEE, June 1992, 80(6), 819-830.
56. Teets, D., A model for radial yield degradation as a function of chip size. IEEE Trans. Semicon. Manuf., 1996, 9(3), 467-471.
57. Thompson, K.M., Intel and the myths of test. IEEE Des. Test Compta., 1996, 13(1), 79-81.
58. Tobin, K.W. and Karnowski, T.P., Technology considerations for future semiconductor data management systems. Semicon. Fabtech. 2005, 12(1), 57-63.
59. Uzsoy, R., Lee, C. and Martin-Vega. L.A., A review of production planning and scheduling models in the semiconductor industry. Part I: system characteristics, performance evaluation and production planning. IIE Trans., 1992, 24(4), 47-60.
60. Van Zant, P., Microchip Fabrication: A Practical Guide to Semiconductor Processing. 2004 (McGraw-Hill: New York, NY).
61. Walker, H., Yield Simulation for Integrated Circuits, 1987 (Kluwer Academic Publishers: Boston, MA).
62. Wang J. and Spanos, J.C. A novel approach for modeling and diagnostics of lithography process. AEC/APC XII Symposium 2001 (submitted).
63. Wolf, S., Microchip Manufacturing, 2003 (Lattice Press: California).
64. Wong, A.Y., Statistical micro yield modeling. Semicon. Int., 1996, 19(12), 139-148.