A model for radial yield degradation as a function of chip size

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 3, 1996, Pages 467-471

  Teets, David ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DEGRADATION; MATHEMATICAL MODELS; SILICON WAFERS; YIELD STRESS;

RADIAL YIELD DEGRADATION; YIELD DATA;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030214993     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.536118     Document Type: Article

References (8)

1. T. Yanagawa, "Influence of epitaxial mounds on the yield of integrated circuits," Proc. IEEE, vol. 57, pp. 1621-1628, Sept. 1969.
2. T. Yanagawa, "Yield degradation of integrated circuits due to spot defects," IEEE Trans. Electron Devices, vol. ED-19, no. 2, 1972.
3. A. Gupta and J. W. Lathrop, "Yield analysis of large integrated circuit chips," IEEE J. Solid-State Circuits, vol. SC7, pp. 389, 1972.
4. A. Gupta, W. A. Porter, J. W. Lathrop, "Defect analysis and yield degradation of integrated circuits," IEEE J. Solid-State Circuits, vol. SC9, 1974.
5. O. Paz and T. R. Lawson, Jr., "Modification of Poisson statistics: Modeling defects induced by diffusion," IEEE J. Solid-State Circuits, vol. SC-12, pp. 540-546, Oct. 1977.
6. C. H. Stapper, "LSI yield modeling and process monitoring," IBM J. Res. Develop., vol. 20, pp. 228-234, May 1976.
7. C. H. Stapper, "Integrated circuit yield statistics," Proc. IEEE, vol. 71, no. 4, Apr. 1983.
8. D. Teets, "A model for intra wafer yield as a function of die size," M.S. thesis, Univ. Colorado, Colorado Springs, July 1995.