In-line yield prediction methodologies using patterned wafer inspection information

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 1, 1998, Pages 40-47

  Nurani, Raman K ^b   Strojwas, Andrzej J ^a,c   Maly, Wojciech P ^a,c   Ouyang, Charles ^c   Shindo, Wataru ^a,d   Akella, Ramakrishna ^a,d   McIntyre, Michael G ^e   Derrett, Jason ^f  

^a IEEE

^b KLA TENCOR CORPORATION   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

^d STANFORD UNIVERSITY   (United States)

^e ADVANCED MICRO DEVICES   (United States)

^f UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Critical area; Defect; In line inspection; Kill ratio; Yield; Yield prediction

Indexed keywords

DEFECTS; INSPECTION; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MANUFACTURE;

CRITICAL AREA MODEL; IN LINE INSPECTION; KILL RATIO MODEL; YIELD PREDICTION;

SILICON WAFERS;

EID: 0031996613     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.661283     Document Type: Article

References (8)

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