Modeling and optimization of wafer radial yield

10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, ASMC 1999

Volumn , Issue , 1999, Pages 71-75

  Maynard, D ^a   Bombardier, S ^a   Cavanaugh, A ^a   Zwonik, R ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECT DENSITY; MANUFACTURE; MICROELECTRONICS; PRODUCT DESIGN; PRODUCTIVITY; SEMICONDUCTOR DEVICE MANUFACTURE;

IBM MICROELECTRONICS; LAYOUT MODIFICATION; MODELING AND OPTIMIZATION; PRODUCTIVITY IMPACTS; RANDOM DEFECT DENSITY; SEMICONDUCTOR INDUSTRY; SEMICONDUCTOR MANUFACTURERS; TOOLING MODIFICATIONS;

SILICON WAFERS;

EID: 33750366352     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.1999.798184     Document Type: Conference Paper

References (2)

1. S B. Sisler, J. P. Bonn, R. C. Whiteside, Steps per wafer reduction for photolithographic tool productivity improvement 8th Annual IEEE/SEMI ASMC, September 1997
2. Charles H. Stapper, "Fact and fiction in yield modeling, " Microelectronics Journal, V01.20, Nos. 1-2, 1989