A 100mW 4×10Gb/s transceiver in 80nm CMOS for high-density optical interconnects

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Kromer, Christian ^a   Sialm, Gion ^a   Berger, Christoph ^b   Morf, Thomas ^b   Schmatz, Martin ^b   Ellinger, Frank ^a   Erni, Daniel ^a   Bona, Gian Luca ^b   Jäckel, Heinz ^a  

^a ETH ZURICH   (Switzerland)

^b IBM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144445669     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Ahadian et. al., "A Quad 2.7Gb/s Parallel Optical Transceiver," IEEE RFIC Symp., pp. 13-16, June, 2004.
2. D. M. Kuchta et al., "120Gb/s VCSEL-Based Parallel-Optical Interconnect and Custom 120Gb/s Testing Station," IEEE J. Lightwave Technology, vol. 22, no. 9, pp. 2200-2212, Sept., 2004.
3. C. Kromer et al., "A Low-Power 20GHz 52dBQ Transimpedance Amplifier in 80nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885-894, June, 2004.