A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 9, 1997, Pages 1430-1438

  Voinigescu, Sorin P ^a,b,f,g,h   Maliepaard, Michael C ^a,b,i,j,k,l   Showell, Jonathan L ^a,b,m,n   Babcock, Greg E ^b   Marchesan, David ^a,b   Schroter, Michael ^a,b,c   Schvan, Peter ^a,b   Harame, David L ^a,d,e  

^a IEEE   (Canada)

^b NORTEL NETWORKS   (Canada)

^c Rockwell Semiconductor Systems   (United States)

^d IBM MICROELECTRONICS   (United States)

^e IBM   (United States)

^f UNIVERSITY POLITEHNICA OF BUCHAREST   (Romania)

^g UNIVERSITY OF TORONTO   (Canada)

^h R and D Department   (Romania)

ⁱ QUEEN S UNIVERSITY   (Canada)

^j UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^k Silicon Proc Technology Department

^l Technol Access and Applic Dept

^m MCMASTER UNIVERSITY   (Canada)

ⁿ NATIONAL RESEARCH COUNCIL CANADA   (Canada)

more..

Author keywords

Bipolar transistor; Compact modeling; Low noise; Low noise amplifier; Low noise transistor design; Noise figure; Noise matching; Noise measurements; Radio frequency integrated circuit design; SiGe heterojunction bipolar transistor

Indexed keywords

AMPLIFIERS (ELECTRONIC); INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE;

LOW NOISE AMPLIFIERS (LNA); NOISE FIGURE;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0031236647     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.628757     Document Type: Article

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