Design and evaluation of a hierarchical decoupled architecture

Journal of Supercomputing

Volumn 38, Issue 3, 2006, Pages 237-259

  Ro, Won W ^a   Crago, Stephen P ^b   Despain, Alvin M ^c   Gaudiot, Jean Luc ^d  

^a CALIFORNIA STATE UNIVERSITY   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^c University of Southern California   (United States)

^d University of California at Irvine   (United States)

Author keywords

Data prefetching; Decoupled architectures; Instruction level parallelism; Memory latency hiding; Multithreading; Parallel architecture; Speculative execution

Indexed keywords

DATA PREFETCHING; DECOUPLED ARCHITECTURES; INSTRUCTION LEVEL PARALLELISM; MEMORY LATENCY HIDING; MULTITHREADING; PARALLEL ARCHITECTURE; SPECULATIVE EXECUTION;

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; PROBLEM SOLVING;

HIERARCHICAL SYSTEMS;

EID: 33749484001     PISSN: 09208542     EISSN: 15730484     Source Type: Journal    
DOI: 10.1007/s11227-006-8321-2     Document Type: Article

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