Synergy of multithreading and access/execute decoupling

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 59-63

  Parcerisa, Joan Manuel ^a   Gonzalez, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SELECTION AND EVALUATION; DATA STORAGE EQUIPMENT; MULTIPROGRAMMING; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

ACCESS/EXECUTE DECOUPLING; INSTRUCTION LEVEL PARALLELISM (ILP); MULTITHREADING;

COMPUTER ARCHITECTURE;

EID: 0032761956     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.1999.744329     Document Type: Conference Paper

References (10)