Exploiting instruction level parallelism with the DS architecture

Proceedings of the International Conference on Parallel Processing

Volumn 1, Issue , 1996, Pages 230-237

  Zhang, Yinong ^a   Adam, G B ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILER TECHNIQUES; COMPLEX HARDWARE; COMPUTATIONAL TASK; CONTROL FLOWS; INSTRUCTION LEVEL PARALLELISM; SUB-STREAMS; SUPERSCALAR; SUPERSCALAR PROCESSOR;

EID: 33749474936     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1996.539060     Document Type: Conference Paper

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