Execution and cache performance of the Scheduled Dataflow architecture

Journal of Universal Computer Science

Volumn 6, Issue 10, 2000, Pages 948-967

  Kavi, Krishna ^a   Anil, Joseph ^a   Giorgi, Roberta ^b  

^a UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

^b UNIVERSITY OF SIENA   (Italy)

Author keywords

Dataflow architectures; Decoupled Architectures; Memory latency; Multithreaded architectures; Superscalars

Indexed keywords

EID: 0000254845     PISSN: 0948695X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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