메뉴 건너뛰기




Volumn 41, Issue 7, 2006, Pages 163-172

Compiler-directed thermal management for VLIW functional units

Author keywords

IPC; Thermal; VLIW

Indexed keywords

POWER OPTIMIZATION; TEMPERATURE MINIMIZATION; THERMAL MANAGEMENT;

EID: 33749026682     PISSN: 03621340     EISSN: 03621340     Source Type: Journal    
DOI: 10.1145/1159974.1134674     Document Type: Article
Times cited : (8)

References (39)
  • 1
    • 84859277051 scopus 로고    scopus 로고
    • http://www.intel.com/products/server/processors/server/itanium/
  • 2
    • 84859283693 scopus 로고    scopus 로고
    • http://www.isonics.com/
  • 3
    • 84859292976 scopus 로고    scopus 로고
    • http://www.itrs.net/Common/2004Update/2004_000_ORTC.pdf
  • 4
    • 84859292977 scopus 로고    scopus 로고
    • http://lava.cs.virginia.edu/HotSpot/index.htm
  • 5
    • 84859278551 scopus 로고    scopus 로고
    • http://www.trimaran.org/
  • 6
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23-29, 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 11
    • 1242283591 scopus 로고    scopus 로고
    • Thermal modeling and measurement of large high-power silicon devices with asymmetric power distribution
    • J. Deeney. Thermal modeling and measurement of large high-power silicon devices with asymmetric power distribution. In Proceedings of the 35th International Symposium on Microelectronics, 2002.
    • (2002) Proceedings of the 35th International Symposium on Microelectronics
    • Deeney, J.1
  • 13
    • 0019596071 scopus 로고
    • Trace scheduling: A technique for global microcode compaction
    • A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478-490, 1981.
    • (1981) IEEE Transactions on Computers , vol.C-30 , Issue.7 , pp. 478-490
    • Fisher, A.1
  • 14
    • 0013035133 scopus 로고    scopus 로고
    • Using IPC variation in workloads with externally specified rates to reduce power consumption
    • S. Ghiasi, J. Casmira, D. Grunwald. Using IPC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexity-Effective Design, 2000.
    • (2000) Workshop on Complexity-effective Design
    • Ghiasi, S.1    Casmira, J.2    Grunwald, D.3
  • 29
    • 33746099460 scopus 로고    scopus 로고
    • The design and implementation of a first-generation CELL Processor: A multi-core supercomputer SoC
    • D. C. Pham. The design and implementation of a first-generation CELL Processor: A multi-core supercomputer SoC. In Proceedings of International Forum on Application Specific MPSoC, 2005.
    • (2005) Proceedings of International Forum on Application Specific MPSoC
    • Pham, D.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.