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Volumn 2003-January, Issue , 2003, Pages 211-216

Microarchitecture level power and thermal simulation considering temperature dependent leakage model

Author keywords

Circuit simulation; Clocks; Helium; Microarchitecture; Permission; Power system modeling; Temperature dependence; Temperature sensors; Thermal engineering; Thermal management

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; HELIUM; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; POWER ELECTRONICS; TEMPERATURE CONTROL; TEMPERATURE DISTRIBUTION; TEMPERATURE SENSORS;

EID: 1542359151     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231864     Document Type: Conference Paper
Times cited : (39)

References (15)
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  • 2
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    • Wattch: A framework for architectural-level power analysis optimization
    • D.Brooks, V.Tiwari, and M.Martonosi, "Wattch: A framework for architectural-level power analysis optimization," in ISCA, 2000.
    • (2000) ISCA
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 4
    • 0036911590 scopus 로고    scopus 로고
    • Leakage power modeling and reduction with data retention
    • W. Liao, J. M. Basile, and L. He, "Leakage power modeling and reduction with data retention," in ICCAD 02, Nov 2002.
    • ICCAD 02, Nov 2002
    • Liao, W.1    Basile, J.M.2    He, L.3
  • 5
    • 0034842158 scopus 로고    scopus 로고
    • Future performance challenges in nanometer design
    • D. Sylvester and H. Kaul, "Future performance challenges in nanometer design," in DAC, 2001.
    • (2001) DAC
    • Sylvester, D.1    Kaul, H.2
  • 8
    • 84962299846 scopus 로고    scopus 로고
    • Evaluating run-time techniques for leakage power reduction techniques
    • D. Duarte, Y. Tsai, N. Vijaykrishnan, and M. J. Irwin, "Evaluating run-time techniques for leakage power reduction techniques," in ASP-DAC, 2002.
    • (2002) ASP-DAC
    • Duarte, D.1    Tsai, Y.2    Vijaykrishnan, N.3    Irwin, M.J.4
  • 12
    • 0031639693 scopus 로고    scopus 로고
    • Reducing power in high-performance microprocessors
    • V. Tiwari, D. Singh, S. Rajgopal, and G. Mehta, "Reducing power in high-performance microprocessors," in DAC, 1998.
    • (1998) DAC
    • Tiwari, V.1    Singh, D.2    Rajgopal, S.3    Mehta, G.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.