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Volumn , Issue , 2003, Pages 1052-1057

Dynamic functional unit assignment for low power

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING POINTS; FUNCTIONAL UNIT ASSIGNMENT; FUNCTIONAL UNITS; HARDWARE SCHEMES; INTEGER VALUES; LEAST-SIGNIFICANT DIGITS; SIGN EXTENSION; SWITCHING ACTIVITIES;

EID: 33749324428     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253743     Document Type: Conference Paper
Times cited : (11)

References (16)
  • 2
    • 0030172836 scopus 로고    scopus 로고
    • Transformation and synthesis of fsms for low power gated clock implementation
    • June
    • L. Benini and G. D. Micheli. Transformation and Synthesis of FSMs for Low Power Gated Clock Implementation. IEEE Transactions on Computer-Aided Design, 15(6):630-643, June 1996
    • (1996) IEEE Transactions on Computer-Aided Design , vol.15 , Issue.6 , pp. 630-643
    • Benini, L.1    Micheli, G.D.2
  • 5
    • 0003465202 scopus 로고    scopus 로고
    • Version 2.0. Technical Report TR 1342, University of Wisconsin, Madison, WI June
    • D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report TR 1342, University of Wisconsin, Madison, WI, June 1997
    • (1997) SimpleScalar Tool Set
    • Burger, D.1    Austin, T.2
  • 7
    • 84893727368 scopus 로고    scopus 로고
    • S. P. E. Corporation
    • S. P. E. Corporation. The SPEC benchmark suites. http://www.spec.org/.
    • SPEC Benchmark Suites
  • 9
    • 0032640861 scopus 로고    scopus 로고
    • Leakage control with efficient use of transistor stacks in single threshold cmos
    • June
    • M. Johnson, D. Somasekhar, and K. Roy. Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. In Design Automation Conference, pages 442-445, June 1999
    • (1999) Design Automation Conference , pp. 442-445
    • Johnson, M.1    Somasekhar, D.2    Roy, K.3
  • 10
    • 0006956822 scopus 로고    scopus 로고
    • Modeling inter-instruction energy effects in a digital signal processor
    • in conjunction with Int?l Symposium on Computer Architecture June
    • B. Klass, D. E. Thomas, H. Schmit, and D. E. Nagle. Modeling Inter-Instruction Energy Effects in a Digital Signal Processor. In Power-Driven Microarchitecture Workshop, in conjunction with Int?l Symposium on Computer Architecture, June 1998
    • (1998) Power-Driven Microarchitecture Workshop
    • Klass, B.1    Thomas, D.E.2    Schmit, H.3    Nagle, D.E.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.