Adapting instruction level parallelism for optimizing leakage in VLIW architectures

ACM SIGPLAN Notices

Volumn 38, Issue 7, 2003, Pages 275-283

  Kim, H S ^a   Vijaykrishnan, N ^a   Kandemir, M ^a   Irwin, M J ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Functional units; Instruction level parallelism; Instruction scheduling; Leakage energy; Power supply gating; VLIW architecture

Indexed keywords

ALGORITHMS; COMPUTER PROGRAMMING LANGUAGES; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SCHEDULING; POWER SUPPLY GRATING;

COMPUTER SYSTEMS PROGRAMMING;

EID: 1442288679     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/780731.780770     Document Type: Conference Paper

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