Load Balancing in Superscalar Architectures

Proceedings - Euromicro Conference on Real-Time Systems

Volumn , Issue , 1996, Pages 651-658

  Chaves Filho, Eliseu M ^a   Fernandes, Edil S T ^a   Wolfe, Andrew ^b  

^a FEDERAL UNIVERSITY OF RIO DE JANEIRO   (Brazil)

^b Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL PROCESSING SYSTEMS;

COMPUTATIONAL LOADS; DYNAMIC INSTRUCTIONS; FUNCTIONAL UNITS; HARDWARE RESOURCES; INSTRUCTION LEVEL PARALLELISM; LOAD-BALANCING; PARALLEL EXECUTIONS; PERFORMANCE; SUPERSCALAR; SUPERSCALAR ARCHITECTURE;

APPLICATION PROGRAMS;

EID: 33746054276     PISSN: 10683070     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1996.546493     Document Type: Conference Paper

References (13)

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